# US 4,398,218 A · Signal monitor system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,398,218 A - Document ID: US4398218A - Status: Granted - Kind: A - Application number: 06/290,647 - Filed: 1981-08-06 - Granted: 1983-08-09 - Earliest claimed: 1977-09-01 - Assignees: Honeywell Inc. - Inventors: William F. Acker - Web page: https://patentgrep.com/patent/US4398218A ## CPC - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H03K 5/153: Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant (switching at zero crossing H03K17/13) - H03K 5/19: Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) - H04L 1/20: using signal quality detector - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Apparatus for identifying intended crossing events of a preselected value of an analog signal is disclosed. The apparatus further identifies whether the signal is rising or falling during those crossing events. ## Claims ### Claim 1 An intended reference level crossing detector means, adapted to receive a data signal formed as a sequence of data samples, having a crossing detector output, said reference level crossing detector means comprising: an incoming signal amplitude range classifier for determining whether said data samples are within certain amplitude ranges and having first and second classifier outputs, said incoming signal amplitude range classifier being capable of providing (i) as a first classifier output signal an indication for each said data sample, at said first classifier output, whether that said data sample has a value that is within a first selected range, and providing (ii) as a second classifier output signal an indication for each said data sample, at said second classifier output, whether that said data sample has a value that is within a second selected range; a high range storage means having a high range storage means input and a high range storage means output, said high range storage means being capable of providing as a high range storage means output signal an indication, at said high range storage means output, whether a said data sample, preceding that said data sample corresponding to a current value of said first classifier output signal, had a value that was within said first selected range, said high range storage means input being connected to said first classifier output; a low range storage means having a low range storage means input and a low range storage means outut, said low range storage means being capable of providing as a low range storage means output signal an indication, at said low range storage means output, whether a said data sample, preceding that said data sample corresponding to a current value of said second classifier output signal, had a value that was within said second selected range, said low range storage means input being connected to said second classifier output; a falling pattern AND logic gate means having first and second falling pattern AND logic gate means inputs and a falling pattern AND logic gate means output, said first falling pattern AND logic gate means input being connected to said second classifier output and said second falling pattern AND logic gate means input being connected to said high range storage means output; a rising pattern AND logic gate means having first and second rising pattern AND logic gate means inputs and a rising pattern AND logic gate means output, said first rising pattern AND logic gate means input being connected to said first classifier output and said second rising pattern AND logic gate means output being connected to said low range storage means output; and a combining OR logic gate means having first and second combining OR logic gate means inputs and a combining OR logic gate means output, said first combining OR logic gate means input being connected to said falling pattern AND logic gate means output and said second combining OR logic gate means input being connected to said rising pattern AND logic gate means output. ### Claim 2 (depends on 1) The intended reference level crossing detector means of claim 1 wherein said low range storage means input serves also as an intended reference level crossing detector means slope direction output. ### Claim 3 (depends on 1) The intended reference level crossing detector means of claim 1 wherein said high range storage means input serves also as an intended reference level crossing detector means slope direction output. ### Claim 4 (depends on 1, 2, 3) The intended reference level crossing detector means of claim 1, claim 2, or claim 3 wherein said high range storage means includes a high range storage means first flip-flop. ### Claim 5 (depends on 4) The intended level crossing detector means of claim 4 wherein said high range storage means further includes a high range storage means second flip-flop, each of said high range storage means first and second flip-flops having an input and an output, said high range storage means first flip-flop input serving as said high range storage means input, and said high range storage means first flip-flop output being connected to said high range storage means second flip-flop input, and said high range storage means second flip-flop output serving as said high range storage means output. ### Claim 6 (depends on 5) The intended reference level crossing detector means of claim 5 wherein said high range storage means first and second flip-flops are D-type flip-flops. ### Claim 7 (depends on 1, 2, 3) The intended reference level crossing detector means of claim 1, claim 2, or claim 3 wherein said low range storage means includes a low range storage means first flip-flop. ### Claim 8 (depends on 7) The intended reference level crossing detector means of claim 7 wherein said low range storage means further comprises a low range storage means second flip-flop, each of said low range storage means first and second flip-flops having an input and an output, said low range storage means first flip-flop input serving as said low range storage means input, and said low range storage means first flip-flop output being connected to said low range storage means second flip-flop input, and said low range storage means second flip-flop output serving as said low range storage means output. ### Claim 9 (depends on 8) The intended reference level crossing detector means of claim 8 wherein said low range storage means first and second flip-flops are D-type flip-flops. ### Claim 10 (depends on 8) The intended reference level crossing detector means of claim 8 wherein said high range storage means includes high range storage means first and second flip-flops, each of said high range storage means flip-flops having an input and an output, said high range storage means first flip-flop input serving as said high range storage means input, and said high range storage means first flip-flop output being connected to said high range storage means second flip-flop input, and said high range storage means second flip-flop output serving as said high range storage means output. ### Claim 11 (depends on 10) The intended reference level crossing detector means of claim 10 wherein all of said flip-flops are D-type flip-flops. ### Claim 12 (depends on 11) The intended reference level crossing detector means of claim 11 wherein said falling pattern AND logic gate means is an AND logic gate and said rising pattern AND logic gate means is an AND logic gate and said combining OR logic gate means is an OR logic gate.