# US 4,398,208 A · Integrated circuit chip package for logic circuits

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- Number: US 4,398,208 A
- Document ID: US4398208A
- Status: Granted
- Kind: A
- Application number: 06/168,226
- Filed: 1980-07-10
- Granted: 1983-08-09
- Earliest claimed: 1979-07-10
- Assignees: Nippon Electric Co., Ltd.
- Inventors: Hiroshi Murano; Moritoshi Akino
- Web page: https://patentgrep.com/patent/US4398208A

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10W 40/226: {characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461)}
- H10W 40/47: by flowing liquids, e.g. forced water cooling
- H10W 70/685: comprising multiple insulating layers
- H10W 76/12: characterised by their shape
- H10W 90/00: Package configurations
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) chip package comprises a plurality of IC chips mounted on a multilayer substrate. A plurality of covers are provided on the substrate and are positioned so as to cover at least one of the IC chips. External pins are provided on each of the covers, and each of the pins is connected to selected chips via first signal lines on the covers connecting the pins to the substrate, and second signal lines within the substrate connecting the first signal lines to the selected chips. The substrate may be provided with a heat exchanger or heat sinks at the underside thereof, the overall construction resulting in a cool operating IC chip package with numerous external terminals having short wiring lengths to the chips.

## Claims

### Claim 1

An integrated circuit (IC) chip package for logic circuits comprising:
a substrate;
a plurality of IC chips mounted on the surface of the substrate;
at least one cover provided on said substrate surface, said cover having a concave rectangular bracket-shaped cross section and positioned so as to cover at least one of said IC chips;
a plurality of external terminals formed on the upper surface of said cover;
a plurality of first signal lines electrically connected to each of the external terminals and positioned independently on said cover; and
a plurality of second signal lines for electrically connecting selected first signal lines to selected IC chips, said at least one cover comprising at least first and second covers each covering different ones of said plurality of IC chips, at least one of said second signal lines being embedded in said substrate and electrically connecting an IC chip under said first cover with a first signal line on said second cover.

### Claim 2 (depends on 1)

An IC chip package for logic circuits as claimed in claim 1, further comprising heat sink means provided on the underside of said substrate for air cooling said IC chip package.

### Claim 3 (depends on 1)

An IC chip package for logic circuits as claimed in claim 1, further comprising heat exchanger means provided on the underside of said substrate for liquid cooling said IC chip package.

### Claim 4 (depends on 1)

An IC chip package for logic circuits as claimed in claim 1, wherein said substrate has a multilayer structure composed of two insulating layers and a conductive layer inserted between said insulating layers, said conductive layer forming said at least one plurality of said second signal lines.

### Claim 5 (depends on 1)

An IC chip package for logic circuits as claimed in claim 1, wherein the upper surface of at least one of said first and second covers is provided with a hole bored therethrough.

### Claim 6 (depends on 1)

An IC chip package for logic circuits as claimed in claim 1, wherein said plurality of external terminals are pin-type terminals.

### Claim 7 (depends on 1)

An IC chip package for logic circuits as claimed in claim 1, wherein said plurality of external terminals are pad-type terminals.