On-chip Delta-I noise clamping circuit
AssigneeInternational Business Machines Corporation
InventorsEvan E. Davidson, George A. Katopis, Barry J. Rubin
Life of this patent
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Abstract
A clamping circuit to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. An impedance path is defined between each of the chips and the power supply to define a current path for switching noise through the top of the module. A high impedance path is defined for voltages below a predetermined upper limit of the chip supply voltage and a low impedance path is defined by the clamping circuit for the voltage range where noise superimposed on the chip supply voltage occurs.
Claims9
In a semiconductor structure having a pair of semiconductor chips each having a pair of power leads, one chip defining a driver communicating with a second chip defining a receiver, a module section packaging and inter-connecting said pair of chips, said module section having a signal plane and two reference planes on either side of said signal plane, a pair of power vias disposed under said pair of chips and coupled to each other through decoupling capacitances, the improvement comprising;
- means coupled between said pair of chip power leads of each chip defining an on-chip impedance characteristic having at least one high impedance region and a low impedance region, for interconnecting the power vias for allowing substantially all module currents to complete current loops on-chip.
A clamping circuit to reduce self-induced switching noise in semiconductor structure comprising;
- a pair of semiconductor chips, a module section packaging and interconnecting said chips, means defining a power supply to said chips and, on-chip means coupled between the leads of said power supply defining a voltage-variable impedance to provide a low impedance current path for switching noise through the top of the module.
In a circuit for reducing self-induced switching noise in a multichip semiconductor structure packaged and interconnected by a module section, a power supply delivering a supply voltage to each chip, the improvement comprising;
- means coupled between the leads of said power supply on said chip defining a high impedance current path for voltages below a predetermined upper limit of chip supply voltage and a low impedance path for a voltage range above said predetermined upper limit where noise superimposed upon said chip supply voltage occurs thereby defining a current path through the top of said module.
Dependencies are inferred from the claim text.