# US 4,398,105 A · Arbiter circuit

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- Number: US 4,398,105 A
- Document ID: US4398105A
- Status: Granted
- Kind: A
- Application number: 06/227,514
- Filed: 1981-01-22
- Granted: 1983-08-09
- Earliest claimed: 1981-01-22
- Assignees: Signetics Corporation
- Inventors: Philip J. Keller
- Web page: https://patentgrep.com/patent/US4398105A

## CPC

- H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)}
- H03K 5/26: the characteristic being duration, interval, position, frequency, or sequence
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An arbiter circuit includes a latch made of two crosscoupled NAND gates, one of which is a Schmitt NAND gate, a difference detector, and two output NOR gates. The output of the latch is coupled to the difference detector and to one input of the NOR gates. The NOR gates receive another input from the difference detector. The difference detector is responsive to a voltage difference that exceeds one V.sub.BE, thereby blocking signals that originate in the latch during oscillating or metastable states of the latch, which may include rut pulses.

## Claims

### Claim 1

An arbiter circuit, comprising:
(a) first and second input terminals and first and second output terminals;
(b) first and second cross-coupled NAND gates coupled to said first and second input terminals, respectively;
(c) a difference detector gate coupled to the outputs of said cross-coupled NAND gates and responsive to a voltage difference exceeding a specified amount;
(d) first and second NOR gates having their outputs coupled to said first and second output terminals, respectively;
(e) means coupling a first input of each of said NOR gates to the output of said difference detector gate, and
(f) means coupling the output of said first NAND gate to a second input of said first NOR gate and coupling the output of said second NAND gate to a second input of said second NOR gate.

### Claim 2 (depends on 1)

The invention according to claim 1, wherein one of said NAND gates comprises a Schmitt trigger NAND gate.

### Claim 3 (depends on 1)

The invention according to claim 1, and further including:
(g) a first inverter coupled to feed back a signal from the output of said first NOR gate to a third input of said second NAND gate, and
(h) a second inverter coupled to feed back a signal from the output of said second NOR gate to a third input of said first NAND gate.

### Claim 4 (depends on 1)

The invention according to claim 1, wherein said difference detector gate is responsive to a voltage difference of about 1 V.sub.BE.