# US 4,398,102 A · Gated parallel decoder

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- Number: US 4,398,102 A
- Document ID: US4398102A
- Status: Granted
- Kind: A
- Application number: 06/232,302
- Filed: 1981-02-06
- Granted: 1983-08-09
- Earliest claimed: 1981-02-06
- Assignees: RCA Corporation
- Inventors: Roger G. Stewart
- Web page: https://patentgrep.com/patent/US4398102A

## CPC

- H03K 19/01742: {by means of a pull-up or down element}
- H03K 19/01721: {by means of a pull-up or down element}
- H03K 19/0948: using CMOS {or complementary insulated gate field-effect transistors}
- H03K 19/0963: {using transistors of complementary type (H03K19/0966 takes precedence)}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The decoder includes a plurality of input signal responsive transistors having their conduction paths connected in parallel between a node and a point of reference potential. These transistors, when turned-on, tend to clamp the node to the reference potential. A controllable load is connected between a second voltage and the node for, when enabled and in the absence of an inhibit signal, providing a conduction path charging the node towards the second voltage. An inhibit network responsive to the node voltage inhibits conduction via the charging conduction path of the load when the node voltage is at, or close to, the second voltage. An external control signal applied to the controllable load can enable it in the absence of the inhibit signal.

## Claims

### Claim 1

The combination comprising:
a plurality of input signal transistors having their conduction paths connected in parallel between a summing node and a circuit point at a first potential, each one of said transistors when turned-on tending to clamp said summing node to said first potential;
a controllable load means connected between said summing node and a second circuit point at a second potential for providing a conduction path for charging said summing node towards said second potential when enabled and in the absence of an inhibit signal;
inhibit means, coupled between said summing node and said controllable load means, responsive to the voltage at said summing node for applying an inhibit signal to said controllable means and preventing conduction via said charging conduction path when the potential at said summing node is approximately equal to said second potential; and
means for applying a control signal to said controllable load means for selectively enabling said controllable load means.

### Claim 2 (depends on 1)

The combination as claimed in claim 1 wherein said inhibit means includes means for:
(a) delaying for a first period of time the application of said inhibit signal to said controllable load means, the first period of time being sufficient to enable the potential at said summing node to become approximately equal to said second potential; and
(b) delaying for a second period of time the removal of said inhibit signal applied to said controllable load means, the second period of time being sufficient to enable the potential at said summing node to become approximately equal to said first potential.

### Claim 3 (depends on 2)

The combination as claimed in claim 2 wherein said controllable load means includes a relatively constant current source.

### Claim 4 (depends on 3)

The combination as claimed in claim 3 wherein said inhibit means including said delaying means includes:
(a) a clamping transistor coupled to said current source for, when turned-on, disabling said current source;
(b) an inverter connected at its input to said summing node and at its output to an output node; and
(c) a delay network connected between said output node and said clamping transistor.

### Claim 5 (depends on 4)

The combination as claimed in claim 4 wherein said controllable load means including said relatively constant current source includes:
(a) an input control inverter connected at its input to said means for applying a control signal to said controllable load means; and
(b) first and second transistors connected at their source electrodes to said second circuit point, the gate and drain of said first transistor and the gate of said second transistor being connected to the output of said input control inverter, and the drain of said second transistor being connected to said summing node.

### Claim 6 (depends on 1)

The combination as claimed in claim 1 further including means applying address inputs to said input signal responsive transistors; and
further including:
a memory array having a word line and a bit line; and
means responsive to the voltage at said summing node for applying a voltage corresponding to the summing node voltage to one of said word and bit line.

### Claim 7

A decoding gate comprising:
a plurality of input signal transistors having their conduction paths connected in parallel between a summing node and a first point of first potential, each one of said transistors, when turned-on, tending to clamp said summing node to said first potential;
a load transistor having a conduction path and a control electrode, means connecting the conduction path of said load transistor between a second circuit point and said summing node;
inhibit means coupled between said summing node and the control electrode of said load transistor for maintaining it turned-off and inhibiting conduction therethrough when the potential at said summing node is approximately equal to the potential at said second circuit point;
a control signal input terminal; and
means coupled between said control signal input terminal and to the gate electrode of said load transistor for turning-on said load transistor in response to the application of a turn on control signal to said control signal input terminal in the absence of an inhibit signal.

### Claim 8 (depends on 7)

The combination as claimed in claim 7 further including means applying address inputs to said input signal transistors, including means for applying said turn on control signal concurrently with the generation of a change in the address inputs to said input signal transistors.

### Claim 9

The combination comprising:
a plurality of input signal transistors, each transistor having a control electrode and a conduction path, means connecting the conduction paths of said plurality of input signal transistors in parallel between a summing node and a circuit point at a first potential, and means connecting the control electrode of each one of said input signal transistor to a different one of a plurality of input lines;
a controllable load means connected between said summing node and a second circuit point at a second potential, said controllable load means being responsive to an externally applied control signal and to a feedback signal derived from said summing node for providing a conduction path charging said summing node to said second potential when said control signal is in an enabling condition and when the potential at said summing node is either approximately equal to the potential at said first point potential or when the potential at said summing node making transition from said first to said second potential.