# US 4,398,100 A · Booster circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,398,100 A - Document ID: US4398100A - Status: Granted - Kind: A - Application number: 06/196,980 - Filed: 1980-10-14 - Granted: 1983-08-09 - Earliest claimed: 1980-03-14 - Assignees: Mitsubishi Denki Kabushiki Kaisha - Inventors: Youichi Tobita; Hiroshi Nishizawa, deceased - Web page: https://patentgrep.com/patent/US4398100A ## CPC - H03K 19/01728: {in synchronous circuits, i.e. by using clock signals} - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A booster circuit in which a signal to be boosted and a boost capacitor are electrically separated during driving periods and are electrically coupled during boosting periods so that the capacitive load which the signal to be boosted must drive is significantly reduced. The boost capacitor is preferably charged to a predetermined voltage level prior to the boosting periods. The coupling means used is preferably an insulated gate FET transistor the gate voltage of which is controlled to be not lower than a power source voltage level before the boosting periods of time. ## Claims ### Claim 1 A booster circuit comprising: a load capacitor coupled to a terminal to which a signal to be boosted is applied; a boost capacitor to which a boosting signal is applied; and means for coupling said signal to be boosted to said boost capacitor only during boosting periods for said signal to be boosted. ### Claim 2 (depends on 1) The booster circuit as defined in claim 1 further comprising means for charging said boost capacitor to a predetermined voltage level before said boosting periods. ### Claim 3 (depends on 1, 2) The booster circuit as defined in claim 1 or 2 wherein said coupling means comprises an insulated gate FET for coupling said signal to be boosted to said boost capacitor. ### Claim 4 A booster circuit comprising: a load capacitor coupled to be driven by a signal to be boosted; a first FET transistor having a first signal electrode coupled to receive said signal to be boosted and a gate electrode coupled to an external voltage source; a second FET transistor having a first signal electrode coupled to receive said signal to be boosted and having a gate electrode coupled to a signal electrode of said first FET transistor; a first boost capacitor coupled between said second signal electrode of said first FET transistor and a source of a boosting signal; a second boost capacitor coupled between a second signal electrode of said second FET transistor and said source of said boosting signal; and a third FET transistor having a first signal electrode coupled to said second signal electrode of said second FET transistor and a second signal electrode and gate electrode coupled to said external voltage source. ### Claim 5 A booster circuit comprising: a load capacitor coupled to be driven by a signal to be boosted; a first FET transistor having a first signal electrode coupled to receive said signal to be boosted and a gate electrode coupled to an external voltage source; a second FET transistor having a first signal electrode coupled to receive said signal to be boosted and having a gate electrode coupled to a signal electrode of said first FET transistor; a first boost capacitor coupled between said second signal electrode of said first FET transistor and a source of a boosting signal; a second boost capacitor coupled between a second signal electrode of said second FET transistor and said source of said boosting signal; a third FET transistor having a first signal electrode coupled to said second signal electrode of said second FET transistor and a second signal electrode coupled to said external voltage source; a fourth FET transistor having a first signal electrode coupled to said external voltage source and a second signal electrode coupled to a gate electrode of said third FET transistor; a fifth FET transistor having a first signal electrode coupled to said gate electrode of said third FET transistor and a second signal electrode coupled to ground; and a capacitor having a first terminal coupled to said gate electrode of said third FET transistor, said signal to be boosted being coupled to a gate electrode of said fifth FET transistor, a control signal being coupled to a second electrode of said capacitor and said control signal inverted being coupled to a gate electrode of said fourth FET transistor. ### Claim 6 A booster circuit comprising: a load capacitor coupled to be driven by a signal to be boosted; a first FET transistor having a gate electrode coupled to receive said signal to be boosted and a first signal electrode coupled to an external voltage source; a second FET transistor having a first signal electrode coupled to receive said signal to be boosted and a gate electrode coupled to a second signal electrode of said first FET transistor; a first boost capacitor coupled between said second signal electrode of said first FET transistor and a source of a boosting signal; a second boost capacitor coupled between a second signal electrode of said second FET transistor and said source of said boosting voltage; a third FET transistor having a first signal electrode coupled to said gate of said second FET transistor, a second signal electrode coupled to ground and a gate electrode coupled to a source of a control signal; and a fourth FET transistor having a first signal electrode coupled to said second signal electrode of said second FET transistor and a second signal electrode and a gate electrode coupled to said external voltage source. ### Claim 7 A booster circuit comprising: a load capacitor coupled to be driven by a signal to be boosted; a first FET transistor having a first signal electrode coupled to receive said signal to be boosted and a gate electrode coupled to an external voltage source; a second FET transistor having a first signal electrode coupled to receive said signal to be boosted and a gate electrode coupled to a second signal electrode of said first FET transistor; a first boost capacitor coupled between said second signal electrode of said first FET transistor and a source of a first boosting signal; a second boost capacitor coupled between said second signal electrode of said second FET transistor and a second source of a boosting signal, the rise of said second boosting signal occurring later in time than the rise of said first boosting signal; and a third FET transistor having a first signal electrode coupled to said second signal electrode of said second FET transistor and a second signal electrode and gate electrode coupled to said voltage source. ### Claim 8 A booster circuit comprising: a load capacitor coupled to be driven by a signal to be boosted; a first FET transistor having a first signal electrode coupled to receive said signal to be boosted; a second FET transistor having a first signal electrode coupled to receive said signal to be boosted and a gate electrode coupled to a second signal electrode of said first FET transistor; a first boost capacitor coupled between said second signal electrode of said first FET transistor and a source of a boosting signal; a second boost capacitor coupled between a second signal electrode of said second FET transistor and said source of a boosting signal; a third FET transistor having a first signal electrode coupled between said second signal electrode of said second FET transistor and a second signal electrode and a gate electrode coupled to an external voltage source; a fourth FET transistor having a first signal electrode coupled to a gate electrode of said first FET transistor and a second signal electrode coupled to said external voltage source; a fifth FET transistor having a first signal electrode coupled to said gate electrode of said first FET transistor and a second signal electrode coupled to ground; a capacitor coupled between a first control signal source and said gate electrode of said first FET transistor, a gate electrode of said fourth FET transistor being coupled to a second control signal source and a gate electrode of said fifth FET transistor being coupled to a third control signal source. ### Claim 9 A booster circuit comprising: a load capacitor coupled to a terminal to which a signal to be boosted is coupled; a first boost capacitor having a first terminal to which a boosting signal is applied; means for coupling said signal to be boosted to said first boost capacitor only during boosting periods for said signal to be boosted and; a second boost capacitor having a first terminal to which said boosting signal is applied and a second terminal connected to a control element of said coupling means for driving said coupling means. ### Claim 10 A booster circuit comprising: a load capacitor coupled to a terminal to which a signal to be boosted is coupled; a first boost capacitor having a first terminal to which first boosting signal is applied; means for coupling said signal to be boosted to said first boost capacitor only during boosting periods for said signal to be boosted; and a second boost capacitor having a first terminal to which a second boosting signal different from said first boosting signal is applied and a second terminal connected to a control element of said coupling means for driving said coupling means.