# US 4,397,075 A · FET Memory cell structure and process

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- Number: US 4,397,075 A
- Document ID: US4397075A
- Status: Granted
- Kind: A
- Application number: 06/165,592
- Filed: 1980-07-03
- Granted: 1983-08-09
- Earliest claimed: 1980-07-03
- Assignees: International Business Machines Corporation
- Inventors: Joseph J. Fatula, Jr.; Paul L. Garbarino
- Web page: https://patentgrep.com/patent/US4397075A

## CPC

- H10B 12/038: {the capacitor being in a trench in the substrate}
- H10B 12/37: {the capacitor being at least partially in a trench in the substrate}
- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10P 50/242: {of Group IV materials}
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A dense, vertical MOS FET memory cell has a high charge storage capacitance per unit area of substrate surface. The charge storage capacitor structure is formed within a well etched in the silicon semiconductor substrate by a combination of reactive ion etching and a self-limiting wet etch.

## Claims

### Claim 1

A method for producing a dense MOS FET memory device having a vertical capacitor comprising
providing a monocrystalline silicon substrate having a gate including a gate dielectric layer on said substrate, a gate electrode layer on said dielectric layer and source and drain regions in said substrate on opposite sides of said gate;
reactive ion etching a substantially U-shaped opening into said substrate in said drain region adjacent to said gate;
growing a silicon dioxide layer on the surface of said U-shaped opening;
reactive ion etching said U-shaped opening deeper into said substrate to form a deeper U-shaped opening;
etching said deeper opening with a directional etchant to form a well having an enlarged buried opening;
removing by etching said silicon dioxide from said well;
diffusing an impurity into the surfaces of said well and;
forming electrical contacts to the source and to said gate electrode layer.

### Claim 2 (depends on 1)

The method of claim 1 wherein the directional etchant is ethylene diamine pyrocatechol.

### Claim 3 (depends on 1)

The method of claim 1 wherein the reactive ion etching of said U-shaped opening is in a fluorine or chlorine containing atmosphere.

### Claim 4 (depends on 1)

The method of claim 1 wherein said substrate is P type silicon and said impurity is N type.

### Claim 5 (depends on 4)

The method of claim 4 wherein said impurity is phosphorus.

### Claim 6 (depends on 4)

The method of claim 4 wherein said impurity is arsenic.

### Claim 7 (depends on 1)

The method of claim 1 wherein said enlarged buried opening has faces lying along the (111) crystal planes of said substrate.

### Claim 8

A method for producing a vertical capacitor comprising:
providing a monocrystalline silicon substrate of a first conductivity type and having a region of a second conductivity type in said substrate;
reactive ion etching a substantially U-shaped opening into said substrate into and through said region of second conductivity type;
growing a silicon dioxide layer on the surface of said U-shaped opening;
reactive ion etching said U-shaped opening deeper into said substrate to form a deeper U-shaped opening;
etching said deeper opening with a directional etchant to form a well having an enlarged buried opening;
removing by etching said silicon dioxide from said well;
diffusing an impurity into the surfaces of said well;
and
forming electrical contact to the said region of second conductivity type.

### Claim 9 (depends on 8)

The method of claim 8 wherein said reactive ion etching of said U-shaped opening is in a fluorine or chlorine containing atmosphere and the said directional etchant is ethylene diamine pyrocatechol.

### Claim 10 (depends on 8)

The method of claim 8 wherein said first conductivity type is P type, said second conductivity type is N type, and said substrate is composed of silicon.

### Claim 11 (depends on 8)

The method of claim 8 wherein said diffusing is done from a phosphosilicate glass layer that has been formed upon the surface of said well.