# US 4,396,995 A · Adapter for interfacing between two buses > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,396,995 A - Document ID: US4396995A - Status: Granted - Kind: A - Application number: 06/238,172 - Filed: 1981-02-25 - Granted: 1983-08-02 - Earliest claimed: 1981-02-25 - Assignees: NCR Corporation - Inventors: Richard S. Grau - Web page: https://patentgrep.com/patent/US4396995A ## CPC - G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's - G06F 13/4059: {where the synchronisation uses buffers, e.g. for speed matching between buses} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An asynchronous interface adapter for interfacing two bidirectional data buses. Data transfer between buses may occur simultaneously with provision made for storing bus data from a first bus until a receiver on the second bus is available. The adapter provides bus requests and grant logic, parity checking, time of day clocking, and is adapted to handle variable-length bus messages with the message bytes being carried in a bit-parallel byte-serial form, asynchronously and generally in a bidirectional manner. ## Claims ### Claim 1 An adapter for coupling a data bus to a peripheral data bus, said data bus and said peripheral data bus being bidirectional, and said adapter having the capability of storing messages received from either bus comprising: a first buffer memory operatively connected between said data bus and said peripheral data bus for communicating data from said data bus to said peripheral data bus; second and third buffer memories operatively connected between said peripheral data bus and said data bus for communicating data from said peripheral data bus to said data bus; control means operatively coupled to each buffer memory for controlling the storage and transmission of data to and from said buffer memories; and clock means operatively coupled to said second and third buffer memories for providing a time tag to each message stored in said second and third buffer memories. ### Claim 2 (depends on 1) The adapter according to claim 1 and further comprising means integral with said second and third buffers for counting the messages stored in said second and third buffer memories; and means operatively coupled to said means for counting and to said data bus for requesting data bus service when the number of counted messages reaches a preselected number corresponding to the limit of messages storable in said second and third buffers. ### Claim 3 (depends on 2) The adapter according to claim 2 and further comprising means operatively coupled to said means for counting for denying access to said second and said third buffer memories when said buffer memories are full by not recognizing requests for buffer memory access appearing on said peripheral data bus. ### Claim 4 (depends on 3) The adapter according to claim 3 and further comprising parity error detector means operatively coupled to said buffer memories for detecting errors in the messages stored in said buffer memories; and status means operatively coupled to and responsive to said parity error detecting means for inserting a signal into the message read from said buffer memories indicating the presence or the absence of a parity error. ### Claim 5 (depends on 4) The adapter according to claim 4 and further comprising: means operatively connected to said second and said third buffer memories for unloading said buffers in the same order that they are loaded. ### Claim 6 An interface adapter for interfacing between a processor and a peripheral device, said interface adapter being coupled to said processor with a data bus and to said peripheral device with a peripheral data bus, said interface adapter comprising: a first buffer memory coupled to said peripheral data bus and to said data bus and capable of storing a plurality of variable length data blocks; means operatively coupled to said first buffer memory for sensing the presence of a preselected number of stored data blocks in said first buffer memory and for initiating a service request condition in the processor coupled to said data bus when said preselected number is sensed; means operatively coupled to said means for sensing and to said peripheral data bus for denying access to said first buffer memory from said peripheral data bus when the preselected number of data blocks are stored in said first buffer memory; control means coupled to said data bus and to said first buffer memory and responsive to control signals from said processor for controlling the transfer of data between said buses; means operatively coupled to said first buffer memory for affixing a time signal to each data block received by said first buffer memory; and a second buffer memory coupled to said peripheral data bus and to said data bus for transferring data from said data bus to said peripheral data bus, said second buffer memory responsive to control signals from said control means for transferring data between said buses. ### Claim 7 (depends on 6) The interface adapter according to claim 6 and further comprising: parity error detector means operatively connected to at least one of said buffer memory means for detecting errors in the data stored in said at least one of said buffer memories; and status means coupled and responsive to said parity error detecting means for inserting a signal with the data read from said at least one of said buffer memories, which signal indicates the presence or the absence of a parity error. ### Claim 8 An adapter for interfacing devices coupled to bidirectional buses comprising: first storage means coupled to said buses and operative to receive and transmit data in a first direction; second storage means coupled to said buses and operative to receive and transmit data in a second direction; means coupled to at least one of said storage means for attaching a time tag to data received by said at at least one of said storage means; means coupled to at least one of said storage means for requesting bus access when said at least one of said storage means has acquired a selected number of blocks of data; and control means operatively coupled to said at least one of said storage means and to said bidirectional buses for effecting a transfer of data from a storage means having a selected number of blocks of data to a bidirectional bus. ### Claim 9 (depends on 8) The adapter according to claim 8 and further comprising: means operatively coupled to at least one of said storage means to said bidirectional buses for denying access to said at least one of said storage means when said at least one of said storage means has acquired a selected number of blocks of data. ### Claim 10 (depends on 8) The adapter according to claim 8 wherein said first and said second storage means are configured to store variable length data blocks. ### Claim 11 (depends on 8) The adapter according to claim 8 and further comprising: parity error detector means operatively coupled to at least one of said storage means for detecting errors in the data stored in said at least one of said storage means; and status means operatively coupled to said parity error detecting means and responsive to said parity error detecting means for inserting a signal with the data read from said at least one of said storage means which signal indicates the presence or the absence of a parity error. ### Claim 12 (depends on 8) The adapter according to claim 8 and further comprising: means for decoding command signals received by said adapter from said buses operatively connected to said first and second storage means and to said means for attaching a time tag for controlling the actuation thereof. ### Claim 13 (depends on 8) The adapter according to claim 8 and further comprising: means operatively coupled to said buffer memories for synchronizing the data transmitted from said adapter to said bidirectional buses.