Combined integrated injection logic and transistor-transistor logic microprocessor integrated circuit design

A microprocessor integrated circuit having a central processing unit which includes

• a. a data path unit comprising independent address data path circuitry and independent ALU data path circuitry, said address data path circuitry and said ALU data path circuitry being simultaneously operational during a clocked cycle;
• b. information bus means operatively connected to said data path unit for supplying address and data information thereto and for receiving address and data information therefrom, said information bus means comprising,
• (i) a bidirectional input/output (I/O) buffer for receiving input information and supplying output information externally of the integrated circuit;
• and
• (ii) a bidirectional I/O multiplexer operatively connected (1) to said I/O buffer for receiving I/O multiplexer input information from said I/O buffer and for supplying I/O multiplexer output information to said I/O buffer, (2) to a bus register multiplexer for supplying address and data information thereto, said bus register multiplexer having multiple inputs thereto including an output of said ALU data path circuitry, said bus register multiplexer being operatively connected to both said data path circuitry and said ALU data path circuitry for selectively directing appropriate address or data information thereto and (3) to a bus multiplexer operatively connected to both said address data path circuitry and to said ALU data path circuitry for receiving multiple output signals from said data path circuitry and selectively directing appropriate of said signals to said I/O multiplexer.