# US 4,396,979 A · Microprocessor with improved arithmetic logic unit data path

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- Number: US 4,396,979 A
- Document ID: US4396979A
- Status: Granted
- Kind: A
- Application number: 06/155,153
- Filed: 1980-05-30
- Granted: 1983-08-02
- Earliest claimed: 1980-05-30
- Assignees: Fairchild Camera and Instrument Corporation
- Inventors: Yeshayahu Mor; Allan M. Schiffman
- Web page: https://patentgrep.com/patent/US4396979A

## CPC

- G06F 9/30: Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22)
- G06F 9/30014: {with variable precision}
- G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30112: {comprising data of variable length}
- G06F 11/2236: {to test CPU or processors}
- G06F 12/14: Protection against unauthorised use of memory {or access to memory}
- G06F 13/36: for access to common bus or bus system
- G06F 21/71: to assure secure computing or processing of information
- G06F 2207/7219: Countermeasures against side channel or fault attacks
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A microprocessor for facilitating the execution of instructions which require repetitive shift and arithmetic logic unit operations comprises an arithmetic logic unit having a first and a second input and an output, a plurality of registers, at least one of which is a bidirectionally shifting register and multiplexing apparatus for selectively coupling each of said plurality of registers to said first and said second inputs and said output of said arithmetic logic unit.

## Claims

### Claim 1

A microprocessor for facilitating the execution of instructions which require repetitive shift and arithmetic logic unit operations comprising:
an arithmetic logic unit having a first and a second input and an output;
a plurality of register means, at least one of which is a bi-directionally shifting register means; and
means for selectively coupling each of said plurality of register means to said first and said second inputs and said output of said arithmetic logic unit.

### Claim 2 (depends on 1)

The microprocessor of claim 1 comprising:
means for repeating an arithmetic logic unit operation and a bi-directionally shifting register means operation and wherein at least one other of said plurality of register means comprises a counting means; and means coupled to said counting means for controlling the number of repetitions of said arithmetic logic unit operation and said bi-directionally shifting register means operation.

### Claim 3 (depends on 2)

The microprocessor of claim 2 comprising:
a shifter; and
means for coupling said shifter to said output of said arithmetic logic unit and to an input of said plurality of register means.