# US 4,396,845 A · Address buffer circuit

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- Number: US 4,396,845 A
- Document ID: US4396845A
- Status: Granted
- Kind: A
- Application number: 06/243,862
- Filed: 1981-03-16
- Granted: 1983-08-02
- Earliest claimed: 1980-03-18
- Assignees: Fujitsu Limited
- Inventors: Tomio Nakano
- Web page: https://patentgrep.com/patent/US4396845A

## CPC

- H03K 3/35606: {with synchronous operation}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 11/4082: {Address Buffers; level conversion circuits}
- H03K 3/356017: {using additional transistors in the input circuit (H03K3/356104, H03K3/3562 take precedence)}
- H03K 19/01855: {synchronous, i.e. using clock signals}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An address buffer circuit for comverting an address signal (A.sub.i) of a TTL level into an address signal (A) of a MOS level an its inverted signal (A) comprising: a pre-amplifier (P-AMP) for receiving the address signal having a TTL level; a main amplifier (M-AMP) comprising a flip-flop (FF.sub.3), a circuit for defining the operation of the flip-flop (FF.sub.3); and an output circuit (OUT) comprised of another flip-flop (FF.sub.4) for producing the address signals of a MOS level. In the pre-amplifier, a depletion type transistor (Q.sub.34) is used as a reference constant current source, which is independent of a power supply voltage (V.sub.DD), for the two values of the address signal of a TTL level.

## Claims

### Claim 1

An address buffer circuit, operatively connectable to receive an address signal of a TTL level and a first clock signal, for converting said address signal of the TTL level into an address signal of a MOS level and its inverted signal, comprising:
first and second power supplies;
a pre-amplifier, operatively connected to said second power supply and having outputs, for receiving the address signal of a TTL level;
a main amplifier, operatively connected to the outputs of said pre-amplifier, having first and second inputs and having outputs and comprising a first flip-flop having a first terminal operatively connected to said first power supply and having a second terminal;
a defining circuit, operatively connected between said first and second power supplies and to said second terminal of said first flip-flop, for defining the potential of said second terminal of said first flip-flop; and
an output circuit, operatively connected to outputs of said main amplifier and comprising a second flip-flop, for producing the address signal of the MOS level and its inverted signal;
wherein said pre-amplifier comprises:
a first transistor of an enhancement type having a drain operatively connected to the first input of said main amplifier, having a source and having a gate operatively connectable to receive the first clock signal;
a second transistor of an enhancement type having a drain operatively connected to the source of said first transistor, a source operatively connected to said second power supply and a gate operatively connectable to receive said address signal of a TTL level;
a third transistor of an enhancement type having a drain operatively connected to the second input of said main amplifier, having a source and having a gate operatively connectable to receive said first clock signal; and
a fourth transistor of a depletion type having a drain operatively connected to the source of said third transistor, and having a gate operatively connected to a source of said fourth transistor and to said second power supply.

### Claim 2 (depends on 1)

An address buffer circuit as set forth in claim 1, wherein said output circuit has standby and active states, and said address buffer circuit further comprising a charging and disconnecting circuit, operatively connected between said main amplifier and said output circuit, for charging said second flip-flop of said output circuit when said output circuit is in the stand-by state and for electrically disconnecting said output circuit from said main amplifier when said output circuit is in the active state.

### Claim 3 (depends on 1)

An address buffer circuit as set forth in claim 1, wherein said first and second transistors are of an enhancement type having first threshold voltage values.

### Claim 4 (depends on 1)

An address buffer circuit as set forth in claim 1, wherein said first flip-flop comprises:
fifth and sixth transistors of a depletion type, each having a source, a drain operatively connected to said first power supply and a gate operatively connected to one of the drains of said first and third transistors respectively; and
seventh and eighth transistors of an enhancement type, each having a drain operatively connected to one of the sources of said fifth and sixth transistors, respectively, a source operatively connected to said second terminal and a gate operatively connected to one of the drains of said eighth and seventh transistors, respectively.

### Claim 5 (depends on 1)

An address buffer circuit as set forth in claim 1, wherein said defining circuit comprises:
a ninth transistor of a depletion type having a drain operatively connected to said first power supply and a gate operatively connected to a source of said ninth transistor and to said second terminal of said first flip-flop; and
a tenth transistor of an enhancement type having a drain operatively connected to the source of said ninth transistor, a source operatively connected to said second power supply and a gate operatively connectable to receive said first clock signal.

### Claim 6 (depends on 2)

An address buffer circuit as set forth in claim 2, wherein said address buffer circuit is operatively connectable to receive a second clock signal, wherein said output circuit has inputs, and wherein said charging and disconnecting circuit comprises:
eleventh and twelfth transistors of an enhancement type having first threshold voltage values, each having a source, a drain operatively connected to the respective one of the outputs of said main amplifier and a gate operatively connected to one of the drains of said twelfth and eleventh transistors, respectively; and
thirteenth and fourteenth transistors of an enhancement type, each having a drain operatively connected to the respective one of the sources of said eleventh and twelfth transistors, a gate operatively connectable to receive the second clock signal and a source operatively connected to the respective one of the inputs of said output circuit.

### Claim 7 (depends on 1)

An address buffer circuit as set forth in claim 1, wherein said address buffer circuit is operatively connectable to receive a second clock signal and a third clock signal which is said second clock signal inverted, and wherein said output circuit comprises:
fifteenth and sixteenth transistors of an enhancement type, each having a source, a drain operatively connectable to receive the third clock signal and a gate operatively connected to the respective one of the outputs of said main amplifier;
seventeenth and eighteenth transistors of an enhancement type, each having a drain operatively connected to the respective one of the sources of said fifteenth and sixteenth transistors, a source operatively connected to a third power supply and a gate operatively connected to one of the drains of said eighteenth and seventeenth transistors, respectively;
nineteenth and twentieth transistors of an enhancement type, each having a drain operatively connected to one of the gates of said fifteenth and sixteenth transistors, respectively, a source operatively connected to said third power supply and a gate operatively connected to one of the drains of said eighteenth and seventeenth transistors, respectively; and
twenty-first and twenty-second transistors of an enhancement type, each having a drain operatively connected to the respective one of the drains of said seventeenth and eighteenth transistors, a source operatively connected to said third power supply and a gate operatively connectable to receive said second clock signal.

### Claim 8 (depends on 2)

An address buffer circuit as set forth in claim 2, wherein said address buffer circuit is operatively connectable to receive a second clock signal and a third clock signal which is said second clock signal inverted, wherein said charging and disconnecting circuit has outputs, and wherein said output circuit comprises:
fifteenth and sixteenth transistors of an enhancement type, each having a source, a drain operatively connectable to receive the third clock signal, and a gate operatively connected to the respective one of outputs of said charging and disconnecting circuit;
seventeenth and eighteenth transistors of an enhancement type, each having a drain operatively connected to the respective one of the sources of said fifteenth and sixteenth transistors, a source operatively connected to a third power supply and a gate operatively connected to one of the drains of said eighteenth and seventeenth transistors, respectively;
nineteenth and twentieth transistors of an enhancement type, each having a drain operatively connected to one of the gates of said fifteenth and sixteenth transistors, respectively, a source operatively connected to said third power supply and a gate operatively connected to one of the drains of said eighteenth and seventeenth transistors, respectively; and
twenty-first and twenty-second transistors of an enhancement type, each having a drain operatively connected to the respective one of the drains of said seventeenth and eighteenth transistors, a source operatively connected to said third power supply and a gate operatively connectable to receive said second clock signal.