# US 4,395,812 A · Forming an integrated circuit

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- Number: US 4,395,812 A
- Document ID: US4395812A
- Status: Granted
- Kind: A
- Application number: 06/270,778
- Filed: 1981-06-05
- Granted: 1983-08-02
- Earliest claimed: 1978-06-13
- Assignees: IBM Corporation
- Inventors: David L. Bergeron; Geoffrey B. Stephens
- Web page: https://patentgrep.com/patent/US4395812A

## CPC

- H10D 30/83: FETs having PN junction gate electrodes
- H10D 84/0107: {Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/406: {Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors}
- H10D 84/409: {Combinations of FETs or IGBTs with lateral BJTs and with one or more of diodes, resistors or capacitors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

## Claims

### Claim 1

In a process for forming an integrated circuit having a plurality of P-type regions formed in the same process step, a first subplurality of which are P-type base regions of vertical NPN transistors, a process for forming JFET device in one of the second subplurality of said plurality of P-type regions, comprising the steps of:
forming an insulating layer on the surface of said base region having first and second windows therein;
simultaneously forming first and second spaced apart N-type regions in said base region through said first and second windows for the JFET source and drain; and
ion implanting an N-type channel region in said base region connected to said source and drain regions;
said P-type base region serving as the gate for the JFET device;
whereby a JFET device may be formed in the base region of an NPN transistor.

### Claim 2 (depends on 1)

The process of claim 1, which further comprises:
forming one P-type region to extend horizontally beyond said first N-type region, with said first N-type region extending horizontally and vertically to separate said one P-type region into first and second P-type portions which are electrically isolated from one another, said first portion being said gate for said JFET device;
forming a third window in said insulating layer over said second P-type portion; and
forming a third N-type region through said third window, as an emitter in an NPN transistor formed with said second P-type portion as the base and said first N-type region serving as the collector thereof;
whereby a series connected JFET and NPN bipolar transistor are formed with said first N-type diffusion serving as the output node thereof.

### Claim 3 (depends on 2)

The process of claim 2 which further comprises:
forming a conductor connecting said first P-type portion to said first N-type region;
whereby said JFET operates as a self-biased load device connected in series with the collector of sand NPN bipolar transistor.

### Claim 4

In a process for forming an integrated circuit having a plurality of P-type regions formed in the same process step, a first subplurality of which are P-type collector regions of graded base lateral PNP transistors, a process for forming a JFET device in one of a second subplurality of said plurality of P-type regions, comprising the steps of:
forming an insulating layer on the surface of said collector region having first and second windows therein;
simultaneously forming first and second spaced apart N-type regions in said base region through said first and second windows for JFET source and drain; and
ion-implanting an N-type channel region in said collector region connected to said source and drain regions;
said P-type collector region serving as the gate for the JFET device;
whereby a JFET device may be formed in the collector region for a double diffused lateral PNP transistor.

### Claim 5 (depends on 4)

The process of claim 4, which further comprises:
forming said one P-type region to extend horizontally beyond said first N-type region, said first N-type region extending horizontally and vertically to separate said one P-type region into first and second P-type portions which are electrically isolated from one another, said first portion being said gate for said JFET device;
forming a third window in said insulating layer over said second P-type portions; and
forming a third N-type region through said third window as a base region and a second P-type region through said third window and contained within said third N-type region as the emitter of a PNP lateral transistor, formed simultaneously with said second P-type portion as the collector thereof;
whereby series connected JFET and lateral PNP bipolar transistors are formed.