Low power CMOS frequency divider

A CMOS frequency divider comprising:

• an even number (K) greater than two of cascaded inverters, each one comprising first and second P channel transistors, third and fourth N channel transistors, means for coupling the source-drain circuits of said P and N channel transistors in series across first and second power supply rails connectable to a source of operating power, means for coupling the gates of said second and third transistors to an inverter input terminal, means for coupling the drain electrodes of said second and third transistors to an inverter output terminal and clock means for alternately switching said first and fourth transistors between conductive and nonconductive states;
• means for bypassing one of said first and fourth transistors in at least one of said inverters by connecting the respective drain to the respective source of said one transistor;
• a combining clocked inverter having K/2 inputs coupled respectively to alternate outputs of said cascaded clocked inverters and an output coupled to the input of the first of said cascaded clocked inverters, said combining clocked inverter comprising:
• K/2 plus one P channel transistors and K/2 plus one N channel transistors, having their source-drain circuits coupled in series between said power supply rails;
• means for coupling the gate electrodes of the P and N channel transistors that have their sources coupled directly respectively to said first and second power supply rails to said clock means for alternately switching said first and fourth transistors;
• and
• means for coupling each of the gates of the remainder of said P channel transistors to a corresponding one of the remainder of said N channel transistor gates, to provide said K/2 inputs.