# US 4,395,754 A · Data processing system having virtual memory addressing

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- Number: US 4,395,754 A
- Document ID: US4395754A
- Status: Granted
- Kind: A
- Application number: 06/180,337
- Filed: 1980-08-22
- Granted: 1983-07-26
- Earliest claimed: 1979-09-28
- Assignees: Siemens Aktiengesellschaft
- Inventors: Wolfgang Feissel
- Web page: https://patentgrep.com/patent/US4395754A

## CPC

- G06F 12/1045: associated with a data cache
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A data processing system has virtual memory addressing and includes a buffer between the working memory and the central processor. The buffer includes a data buffer divided into a plurality of banks of identical size and a plurality of tag/flag memories respectively assigned to the data banks for storing the page address. The data buffer bank and the tag/flag memories are additionally addressed, beyond the page class address, with as many further, directly connected address bits of a virtual page address as are required for the binary addressing of the individual data buffer banks. The virtual partial addressing of the buffer provides a simple addressing for the case in which memory modules of the buffer banks have a capacity beyond the page size.

## Claims

### Claim 1

In a data processing system of the type having virtual addressing and in which a central processor includes a first address register comprising a lower-order portion for receiving real class addresses, and a higher-order portion for receiving virtual page addresses, and an address translation memory means for converting virtual page addresses into real page addresses, and in which a buffer memory is connected between the central processor and a working memory of the system and includes a second address register for receiving real page addresses, a third address register for receiving real class addresses, a data buffer comprising a plurality of equal size data banks connected to and accessed by the third address register, a plurality of tag/flag memories respectively assigned to the data banks and connected to the third address register and connected to the address translation means for storing real page addresses, and comparison means connected to compare the translated page addresses with the page addresses in the tag/flag memories and emit a data bank selection signal to a data bank multiplexer in response to equality of the addresses, the improvement therein comprising:
predetermined higher-order locations in the higher-order portion of the first address register for receiving and storing additional virtual address bits of virtual addresses, which additional virtual address bits are directly connected with the real page class addresses and are equal in number to the bits required for addressing each data bank and its associated tag/flag memory and which are provided in addition to a real class address;
a section of said third address register connected to said first address register to receive the bits stored in said predetermined higher-order locations and transfer said additional virtual address bits to said data banks; and
duplicate tag/flag memories respectively assigned to the tag/flag memories and connected to said third address register and to said address translation memory means for addressing with both the real class addresses and the additional real page addresses obtained by translation of the additional virtual address bits.

### Claim 2 (depends on 1)

The improved data processing system of claim 1, and further comprising:
a plurality of comparison circuits each connected to a respective duplicate tag/flag memory and connected to said address translation memory means for comparing the duplicate tag/flag memory output with the translated address not including the additional virtual address bits.