# US 4,395,726 A · Semiconductor device of silicon on sapphire structure having FETs with different thickness polycrystalline silicon films

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 4,395,726 A
- Document ID: US4395726A
- Status: Granted
- Kind: A
- Application number: 06/134,678
- Filed: 1980-03-27
- Granted: 1983-07-26
- Earliest claimed: 1979-03-30
- Assignees: Tokyo Shibaura Denki Kabushiki Kaisha
- Inventors: Kenji Maeguchi
- Web page: https://patentgrep.com/patent/US4395726A

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 86/03: wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
- H10D 86/427: {having different thicknesses of the semiconductor bodies in different TFTs}
- H10D 86/40: characterised by multiple TFTs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device has a plurality of field effect transistors on an insulating substrate. A semiconductor film constituting at least one of the plurality of field effect transistors is thinner than a semiconductor film of the other field effect transistor or transistors.

## Claims

### Claim 1

A semiconductor device including an insulating substrate, a first silicon film on said substrate to form a depletion mode field effect transistor on said substrate, said first silicon film comprising a source, drain and channel of one conductivity type, a second silicon film on said substrate to form an enhancement mode field effect transistor formed on said substrate, said second silicon film comprising a source and drain of said one conductivity type and a channel of opposite conductivity type, with the source of said depletion mode transistor formed integral with the drain of said enhancement mode transistor, and with the thickness of said first silicon film which constitutes said depletion mode transistor being thinner than said second silicon film which constitutes said enhancement mode transistor.

### Claim 2 (depends on 1)

A semiconductor device of claim 1 wherein the drain of said enhancement mode transistor is connected to the gate of said depletion mode transistor to form an E/D inverter.