# US 4,395,681 A · System for compensating the offset voltage of a differential amplifier

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- Number: US 4,395,681 A
- Document ID: US4395681A
- Status: Granted
- Kind: A
- Application number: 06/219,543
- Filed: 1980-12-23
- Granted: 1983-07-26
- Earliest claimed: 1980-01-09
- Assignees: International Business Machines Corporation
- Inventors: Robert Hornung; Gerard Lebesnerais
- Web page: https://patentgrep.com/patent/US4395681A

## CPC

- H03F 3/45479: {characterised by the way of common mode signal rejection}
- G01R 17/06: Automatic balancing arrangements
- H03F 2200/261: Amplifier which being suitable for instrumentation applications
- H03F: AMPLIFIERS
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A system is disclosed for compensating for the offset voltage problem which occurs in certain types of differential amplifiers; a differential amplifier, in the form of an operational amplifier, is provided with two generators of input signals whose difference is to be amplified; further included is an offset voltage compensation loop comprising a comparator, an n-bit up/down counter and a digital analog converter means; the output of said means being connected to said generators of input signals so as to modulate the input signals; and said digital analog converter means including first and second n-1 bit digital analog converters.

## Claims

### Claim 1

A system for compensating the offset voltage of a differential amplifier comprising:
an operational amplifier provided with two generators of input signals whose difference is to be amplified;
an offset voltage compensation loop, including a comparator, an n-bit up/down counter, and a digital-analog converter means; the output of said comparator being connected to the input of said n-bit up/down counter, and the outputs of said counter being connected to the inputs of said digital-analog converter means;
said digital-analog converter means including first and second n-1 bit digital-analog converters, the output of each converter being connected respectively to one of said generators of input signals so as to modulate the input signals; and in which the inputs of said first converter are connected to the complementary outputs of n-1 bits of said counter, and the inputs of said second converter are connected to the real outputs of said n-1 bits of said counter.

### Claim 2 (depends on 1)

A system as defined in claim 1 in which said first and second converters are connected to supply currents i.sub.1 and i.sub.2 respectively to said generators, said converters being arranged symmetrically with respect to the n-bit up-down counter, and means for ensuring that said converters operate in complementary mode, that is, i.sub.1 +i.sub.2 =1, i being a predetermined constant current.

### Claim 3 (depends on 1)

A system as defined in claim 1 in which n equals 5.

### Claim 4 (depends on 1)

A system as defined in claim 1 further comprising means for inhibiting said first and second converters, said means including gates whose inputs are respectively the most significant bit of a counter and its complement, and whose AND-dotted outputs are respectively connected to the complementary outputs and to the real outputs of said counter.

### Claim 5 (depends on 1)

A system as defined in claim 1 in which each of the first and second converters includes four cells, each cell having four collectors.

### Claim 6 (depends on 5)

A system as defined in claim 5, further including a fifth cell in said second converter to provide for an additional least significant bit.