# US 4,395,644 A · Drive circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,395,644 A - Document ID: US4395644A - Status: Granted - Kind: A - Application number: 06/177,552 - Filed: 1980-08-13 - Granted: 1983-07-26 - Earliest claimed: 1979-08-15 - Assignees: Nippon Electric Co., Ltd. - Inventors: Tetsuo Misaizu - Web page: https://patentgrep.com/patent/US4395644A ## CPC - H03K 19/018514: {with at least one differential stage (H03K19/018528 and H03K19/018542 take precedence)} - H03K 5/023: {using field effect transistors} - H03K 19/01714: {by bootstrapping, i.e. by positive feed-back} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A boot strap type circuit which can raise an output potential up to a power supply voltage irrespective of a condition of an input signal is disclosed. The circuit is characterized by comprising a series circuit coupled between a first end of a capacitor, from which end a boot strapped voltage is derived, and a reference voltage, the series circuit being responsive to transition of the input signal for pulling down a potential at the first end of the capacitor after a predetermined delay from that transition. ## Claims ### Claim 1 A circuit comprising a first insulated gate field effect transistor, a drain node of said first transistor being connectable to a drain voltage, a second insulated gate field effect transistor, a source node of said first transistor and a drain node of said second transistor being electrically common, the source node of said second transistor being connectable to a source voltage, a gate node of said first transistor being capacitively coupled to the source node thereof by a capacitance, a signal node, and a control circuit responsive to signal levels at said signal node for making said first transistor and said second transistor conducting and non-conducting, respectively, thereby producing a voltage larger than said drain voltage in absolute value at the gate node of said first transistor, said control circuit including a third insulated gate field effect transistor, having a gate for receiving a signal of substantially the same phase as a signal at said signal node and having a drain connected to the gate node of said first transistor, a fourth insulated gate field effect transistor having a gate for receiving a signal of substantially the same phase as a signal at said signal node and having a drain coupled to a source of said third transistor and a source connectable to the source voltage, a fifth insulated gate field effect transistor having a gate for receiving a signal having a phase opposite that of a signal at said signal node and having a source coupled to the gate node of said first transistor and a drain connectable to the drain voltage, whereby said fifth transistor is conducting for a first level at the signal node, and is non-conducting for the second level at the signal node, said fourth transistor is conducting in response to a second level at said signal node said third transistor is conducting after said fourth transistor becomes conducting. ### Claim 2 (depends on 1) The circuit according to claim 1, further comprising a sixth insulated gate field effect transistor having a drain connectable to the source of said first transistor and a source connectable to the source voltage and fourth means for supplying a gate of said sixth transistor with a signal delayed from the signal at said signal node. ### Claim 3 (depends on 2) The circuit according to claim 2, further comprising a output terminal and a push-pull circuit having a first input node receiving a signal from the gate node of said first transistor, a second input node receiving a signal from the gate node of said second transistor and an output node coupled to said output terminal. ### Claim 4 (depends on 3) The circuit according to claim 3, further comprising an inverter circuit having an input node coupled to said signal node and an output node coupled to the gate of said fifth transistor. ### Claim 5 (depends on 4) The circuit according to claim 4, further comprising a direct circuit connection coupled between said signal node and the gate of said fourth transistor. ### Claim 6 (depends on 5) The circuit according to claim 5, further comprising a seventh insulated gate field effect transistor having a drain connectable to the drain voltage and a source coupled to the source of said third transistor and a direct circuit connection coupled between said signal node and the gate of said fourth transistor. ### Claim 7 In a circuit where an output is raised up to a power supply voltage by pulling up a gate potential of an output state transistor higher than the power supply voltage by a boot strap effect derived from one end of a capacitor, the improvement comprising a first transistor having a gate receiving a signal which is in the same phase as an input signal to the circuit and connected between the other end of said capacitor and a reference voltage source, and a series circuit including second and third transistors disposed in series between said one end of the capacitor and said reference voltage source, said third transistor having a gate for receiving a signal which has the same phase as said input signal and said second transistor having a gate for receiving a signal having substantially the same phase as said input signal, whereby a potential drop at said one end of the capacitor is reduced by said series circuit. ### Claim 8 (depends on 7) The circuit according to claim 7, in which the signal which the gate of said first transistor receives is also applied to gates of said second and third transistors. ### Claim 9 (depends on 7) The circuit according to claim 7, further comprising a fourth transistor coupled between said power supply voltage and an intermediary node of said series circuit. ### Claim 10 (depends on 9) The circuit according to claim 9, in which said fourth transistor is a depletion type insulated gate field effect transistor and a gate of said fourth transistor is connected to said intermediary node. ### Claim 11 (depends on 9) The circuit according to claim 9, in which said fourth transistor is an enhancement type insulated gate field effect transistor and a gate of said fourth transistor is provided with a signal having an opposite phase to said input signal. ### Claim 12 A circuit comprising a first node, a second node, a first transistor having a gate coupled to said first node and a source coupled to said second node, capacitor means having one end coupled to said first node and the other end coupled to said second node, switching means responsive to a first level of an input signal for substantially changing a potential at said second node to a reference voltage, and control means in responsive to the first level of said input signal for substantially changing a potential at said first node to the reference voltage with a predetermined delay from a time point when said second node is changed towards the reference voltage by said switching means. ### Claim 13 (depends on 12) The circuit according to claim 12, further comprising means for connecting a drain of said first transistor to a power voltage. ### Claim 14 (depends on 13) The circuit according to claim 13, in which said switching means includes a second transistor having a drain coupled to said second node and a source supplied with the reference voltage. ### Claim 15 (depends on 14) The circuit according to claim 14, in which said control means includes a series circuit of a third and a fourth transistors. ### Claim 16 (depends on 15) The circuit according to claim 15, in which said control means further includes a circuit connection connected between a gate of said fourth transistor and a node to which said input signal is applied, and a delay circuit having an input terminal receiving a signal derived from said second node and an output terminal connected to a gate of said third transistor. ### Claim 17 A circuit comprising a first terminal to which a first potential is applied, a second terminal to which a second potential is applied, a first node, a second node, an input terminal, a first insulated gate field effect transistor connected between said first terminal and said second node and having a gate connected to said first node, a capacitor coupled between said first node and said second node, second and third insulated gate field effect transistors each connected between said second node and said second terminal, a first inverter having an input node coupled to said input terminal and an output node, a fourth insulated gate field effect transistor coupled between said first terminal and said first node and having a gate coupled to the output node of said first inverter, a series circuit coupled between said first node and said second terminal, said series circuit including fifth and sixth field effect transistors connected in series, a gate of said sixth transistor being connected to said input terminal, a buffer circuit having an input node coupled to said second node and an output node, and a second inverter having an input node coupled to the output node of said buffer circuit and an output node, gates of said third and fifth transistors being connected to the output node of said second inverter, a gate of said second transistor being connected to said input terminal. ### Claim 18 (depends on 17) The circuit according to claim 17, further comprising a seventh insulated gated field effect transistor coupled between said first terminal and an intermediate junction of said fifth and sixth transistors. ### Claim 19 (depends on 18) The circuit according to claim 18, in which said buffer circuit includes eight and ninth insulated gate field effect transistors connected in series between said first and second terminals. ### Claim 20 (depends on 18) The circuit according to claim 18, further comprising a third inverter having an input node connected to the output node of said second inverter and an output node, and a tenth insulated gate field effect transistor coupled between said first terminal and said first node and having a gate coupled to the output node of said third inverter. ### Claim 21 A circuit comprising a first terminal to which a first potential is applied, a second terminal to which a second potential is applied, a first node, a second node, an input terminal, a first insulated gate field effect transistor connected between said first terminal and said second node and having a gate connected to said first node, a capacitor coupled between said first node and said second node, second and third insulated gate field effect transistors each connected between said second node and said second terminal, a first inverter having an input node coupled to said input terminal and an output node, a fourth insulated gate field effect transistor coupled between said first terminal and said first node and having a gate coupled to the output node of said first inverter, a series circuit coupled between said first node and said second terminal, said series circuit including fifth and sixth field effect transistors connected in series, gates of said fifth and sixth transistors being connected to said input terminal, a buffer circuit having an input node coupled to said second node and an output node, and a second inverter having an input node coupled to the output node of said buffer circuit and an output node, a gate of said third transistor being connected to the output node of said second inverter, a gate of said second transistor being connected to said input terminal. ### Claim 22 (depends on 21) The circuit according to claim 21, further comprising a seventh insulated gate field effect transistor coupled between said first terminal and an intermediate junction of said fifth and sixth transistors. ### Claim 23 (depends on 22) The circuit according to claim 22, in which a gate of said seventh transistor is connected to the output node of said first inverter. ### Claim 24 (depends on 21) The circuit according to claim 21, further comprising an eighth insulated gate field effect transistor coupled between said first terminal and said first node, a third inverter having an input node connected to the output node of said second inverter and an output node connected to a gate of said eighth transistor. ### Claim 25 A circuit comprising a first terminal to which a first potential is applied, a second terminal to which a second potential is applied, first and second insulated gate field effect transistors connected in series between said first and second terminals, a first node, a second node, a gate of said first transistor being connected to said first node, an intermediate junction of said first and second transistors being connected to said second node, said first node being capacitively coupled to said second node, a signal node, and a control circuit responsive to signal levels at said signal node for operatively producing a voltage larger than said first potential at said first node, said control circuit including third and fourth insulated gate field effect transistors connected in series between said first node and said second terminal, said fourth transistor being adapted to take a conducting state when a signal level at said signal node makes said second transistor conducting, said third transistor being adapted to take a conducting state after said fourth transistor is turned to conducting. ### Claim 26 (depends on 25) The circuit according to claim 25, further comprising a fifth insulated gate field effect transistor coupled between said first terminal and an intermediate junction of said third and fourth transistors.