# US 4,395,136 A · Electronic timer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 4,395,136 A
- Document ID: US4395136A
- Status: Granted
- Kind: A
- Application number: 06/223,326
- Filed: 1981-01-08
- Granted: 1983-07-26
- Earliest claimed: 1980-01-17
- Assignees: Matsushita Electric Works, Ltd.; Matsushita Electric Industrial Co., Ltd.
- Inventors: Kenichi Yoda; Hideo Togawa; Eizou Ogawa; Masao Kayahara
- Web page: https://patentgrep.com/patent/US4395136A

## CPC

- H03K 17/28: Modifications for introducing a time delay before switching (modifications to provide a choice of time-intervals for executing more than one switching action H03K17/296)
- G04F 1/005: {using electronic timing, e.g. counting means (pulse time delay arrangements H03K5/13; modifications of electronic switches for introducing a time delay before switching H03K17/28)}
- G04G 3/02: Circuits for deriving low frequency timing pulses from pulses of higher frequency (pulse frequency dividers in general H03K23/00 - H03K29/00)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S)
- G04G: ELECTRONIC TIME-PIECES

## Abstract

An electronic timer wherein a counting circuit for counting outputs of a CR oscillating circuit comprises a plurality of partial counting circuits which are cascade-connected with one another, the respective partial counting circuits are automatically reset by an automatic resetting circuit when a source current voltage is applied or reset by an external resetting circuit at a desired time, the outputs of the CR oscillating circuit are counted by the respective partial counting circuits after the resetting, and a following output circuit is driven when the count reaches an externally set value of a setting circuit. The partial counting circuits are divided into groups by an external driving test circuit to quickly test the operation of the counting circuit.

## Claims

### Claim 1

An electronic timer comprising a CR oscillating circuit, a counting circuit including a plurality of partial counting circuits connected in cascade to one another for counting oscillated outputs of said CR oscillating circuit, an output circuit driving an associated following circuit in response to an output selected out of outputs from one of said partial counting circuits in the final stage of said cascade connection, an automatic resetting circuit for automatically resetting said plurality of partial counting circuits of said counting circuit upon an application of a source current, an external resetting circuit for resetting the partial counting circuits in response to an external signal, a test circuit for dividing said plurality of partial counting circuits into a plurality of groups, and a test signal generating circuit for inspecting the function of each of said divided groups by externally driving said test circuit, said external resetting circuit and said test signal generating circuit being formed of a common circuit comprising first and second inverting circuits receiving a common external signal and respectively having a low inverting threshold value and a high inverting threshold value so that, when said external signal reaches only said low inverting threshold value, a signal driving said test circuit will be provided and, when the external signal reaches said high inverting threshold value, an external resetting signal resetting said plurality of partial counting circuits of said counting circuit will be provided.

### Claim 2 (depends on 1)

An electronic timer according to claim 1 wherein said CR oscillating circuit is stopped in response to an input to said output circuit.

### Claim 3 (depends on 2)

An electronic timer according to claim 2 wherein said CR oscillating circuit is formed of MOS transistors.

### Claim 4 (depends on 3)

An electronic timer according to claim 3 wherein said CR oscillating circuit comprises a capacitor, a first differential circuit providing an output in response to a high charging voltage of said capacitor, a second differential circuit providing an output in response to a low charging voltage of the capacitor, an RS flip-flop actuated in response to said outputs of said first and second differential circuits and providing an output to said counting circuit, and a resistance charging and discharging said capacitor in response to said output of said RS flip-flop.

### Claim 5 (depends on 4)

An electronic timer according to claim 4 wherein said first differential circuit comprises a first series circuit of a first P-MOS transistor and first N-MOS transistor connected at the gate to said capacitor, a second series circuit of a second P-MOS transistor connected at the gate to the gate of said first P-MOS transistor and its own source and second N-MOS transistor connected at the gate to a constant voltage source and a third N-MOS transistor inserted between said first and second series circuits and a direct current source, and said second differential circuit comprises a third series circuit of a third P-MOS transistor connected at the gate to another constant voltage source and fourth N-MOS transistor, a fourth series circuit of a fourth P-MOS transistor connected at the gate to the capacitor and fifth N-MOS transistor connected at the gate to the source and gate of said fourth N-MOS transistor and a fifth P-MOS transistor inserted between said third and fourth series circuits and a direct current source.

### Claim 6 (depends on 5)

An electronic timer according to claim 5 wherein the ratios W/L of the gate width W to the gate length L of said first to fifth P-MOS transistors and first to fifth N-MOS transistors are respectively substantially in the range of 12.5(1+0.25), 12.5(1+0.25), 20(1+0.25), 20(1+0.25), 6(1+0.25), 10(1+0.25), 20(1+0.25), 7.5(1+0.25), 10.5(1+0.25) and 10.5(1+0.25), and said gate length L is about 4 to 8.mu..

### Claim 7 (depends on 2)

An electronic timer according to claim 2 wherein said automatic resetting circuit comprises a fifth series circuit of a sixth N-MOS transistor connected at the gate to a direct current source and at the substrate to its own source and seventh N-MOS transistor connected at the gate to said direct current source and a sixth series circuit of a sixth P-MOS transistor earthed at the gate and eighth N-MOS transistor connected at the gate to the source of said sixth N-MOS transistor.

### Claim 8 (depends on 7)

An electronic timer according to claim 7 wherein said sixth P-MOS transistor and seventh N-MOS transistor are of an impedance of about 50 to 150 K.OMEGA., the ratio W/L of the gate width W to the gate length L of said sixth and eighth N-MOS transistors is substantially in the range of 20(1+0.5), and said gate length L is about 4 to 8.mu..