US 4,394,763 A · Error-correcting system

Abstract

An error-correcting system is disclosed, which is located between a main memory and a central processing unit. The system includes a relief bit memory, an ECC or Error Correction Code logic circuit, a switching circuit and a correction controlling circuit. The ECC logic circuit detects the occurrence of a soft error and a hard error. When a hard error occurs in the memory, the defective memory cell thereof is switched to the relief bit memory. Accordingly, data to be written into the main memory or the relief bit memory is switched by means of the switching circuit. Similarly, data to be read from the main memory or the relief bit memory is also switched by the switching circuit. The data to be stored in the relief bit memory is validated by means of the ECC logic circuit and the switching circuit. Further, the (n+1)-bit soft and hard errors are reduced to n-bit soft and hard errors by means of the ECC logic circuit and the switching circuit.

Claims11

Dependent claims

An error-correcting system, operatively connected between a main memory and a central processing unit, comprising:

an error correction code logic circuit, which can correct n-bit errors, where n is a positive integer, and detect n+1-bit errors;
first means, operatively connected to said central processing unit and said error correction code logic circuit, for discriminating whether an error, occurring in said main memory, is a soft error or a hard error;
second means for storing data for a defective memory cell of said main memory, which defective memory cell produces the hard error;
third means, operatively connected to said main memory, said first means and said second means, for, when a hard error is found by using said first means, switching the data for the defective memory cell of said main memory to said second means;
and
fourth means, operatively connected to said first means and said third means, for effecting a validation operation with respect to the data to be stored in said second means.

3 more elements

Dependencies are inferred from the claim text.

Error-correcting system

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Error-correcting system

Life of this patent

Abstract

Claims11