# US 4,394,758 A · Synchronizing unit for receiving section of PCM station

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- Number: US 4,394,758 A
- Document ID: US4394758A
- Status: Granted
- Kind: A
- Application number: 06/278,065
- Filed: 1981-06-29
- Granted: 1983-07-19
- Earliest claimed: 1980-06-30
- Assignees: Italtel Societa Italiana Telecomunicazioni S.p.A.
- Inventors: Roberto D. Donne
- Web page: https://patentgrep.com/patent/US4394758A

## CPC

- H04L 7/0083: {taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks}
- H04J 3/0605: {Special codes used as synchronising signal}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)

## Abstract

Incoming data words organized in a succession of multi-channel frames, arriving at a receiving section of a PCM station, are fed in parallel therewith to a correlation circuit forming part of a synchronizing unit which includes a timer stepped by line-clock pulses extracted from the incoming bit stream. The correlation circuit includes a decoder which recognizes predetermined bits or bit combinations in alignment words A and B respectively appearing at the beginning of alternate frames. Recurrent noncoincidences of either of these alignment words with a corresponding marking pulse emitted by the timer, in a time slot designating the No. 0 channel of a frame, causes a readjustment of the timer and thus a shifting of clock signals emitted thereby to the receiving section. The synchronizing unit, embodied in an integrated-circuit chip, further includes a malfunction detector responsive to signals emitted by the timer and by the decoder of the correlation circuit.

## Claims

### Claim 1

A synchronizing unit controlling the operation of a receiving station of a PCM station of a telecommunication system, comprising:
timing means stepped by line-clock pulses extracted from an incoming bit stream organized into alternating first and second frames each containing a multiplicity of channels accommodating respective data words, an initial channel No. 0 of each first and second frame normally containing a respective alignment word A and B characterized by at least one invariable bit in a predetermined time position, and timing means generating clock signals fed to said receiving section and further emitting first and second marking pulses TA and TB in a time slot assigned to the No. 0 channel of said first and second frames, respectively;
correlation means including a decoder receiving said incoming bit stream and emitting respective identification pulses AX and BX upon recognizing said alignment words A and B, said correlation means further including logic circuitry generating an error signal FAT upon noncoincidence of said marking pulses TA and TB with the respective identification pulses AX and BX, said logic circuitry feeding corrective signals into said timing means for readjusting same to re-establish coincidence between said marking pulses and the corresponding identification pulses; and
a malfunction detector connected to said correlation means and to said timing means for receiving therefrom at least one of said identification pulses and the corresponding marking pulse, said detector including gating means for producing an alarm indication AW in the absence of coincidence therebetween.

### Claim 2 (depends on 1)

A synchronizing unit as defined in claim 1 wherein said logic circuitry includes first and second counters respectively stepped by said marking pulses TA and TB, a first gate receiving said identification and marking pulses AX and TA for emitting a first alignment pulse ATA upon coincidence thereof, a second gate receiving said identification and marking pulses BX and TB for emitting a second alignment pulse BTB upon coincidence thereof, said first counter having a resetting input connected to said first gate for clearing by said first alignment pulse, said second counter having a resetting input connected to said second gate for clearing by said second alignment pulse, and bistable means settable by either of said counters upon attainment of a predetermined count for generating said error signal.

### Claim 3 (depends on 2)

A synchronizing unit as defined in claim 2 wherein said logic circuitry further comprises a first flip-flop switchable by said first alignment pulse ATA in the set state of said bistable means for generating one of said corrective signals, and a second flip-flop settable by said second alignment pulse BTB for enabling a resetting of said bistable means by a recurrence of said first alignment pulse ATA, said second flip-flop being resettable by said first alignment pulse ATA substantially concurrently with the switching of said first flip-flop for preventing the resetting of said bistable means by said recurrence in the absence of an intervening second alignment pulse BTB.

### Claim 4 (depends on 3)

A synchronizing unit as defined in claim 3 wherein said logic circuitry further comprises a third flip-flop settable by said first alignment pulse ATA simultaneously with the resetting of said second flip-flop for preventing another resetting of the latter by the recurrence of said first alignment pulse ATA, said third flip-flop being resettable by said recurrence in the reset state of said second flip-flop.

### Claim 5 (depends on 1, 2, 3, 4)

A synchronizing unit as defined in claim 1, 2, 3 or 4 wherein said malfunction detector further includes a D-type flip-flop with a data input connected to said gating means for registering any noncoincidence of said first identification pulse AX with said first marking pulse TA, said D-type flip-flop having a clock input receiving said first marking pulse TA from said timing means via a delay line bypassing said gating means.

### Claim 6 (depends on 2, 3, 4)

A synchronizing unit as defined in claim 2, 3 or 4 wherein said predetermined count equals three for each of said counters.

### Claim 7 (depends on 1, 2, 3, 4)

A synchronizing unit as defined in claim 1, 2, 3 or 4 wherein said malfunction detector further includes pulse-counting means stepped by a noncoincidence pulse from said correlation means and controlled by said timing means for generating a high-error-rate signal EPT upon the number of noncoincidence pulses within a predetermined multiframe interval exceeding a given limit a certain number of times in a series of such intervals.

### Claim 8 (depends on 7)

A synchronizing unit as defined in claim 7 wherein said pulse-counting means comprises an m-pulse counter and an n-stage shift register in cascade with each other, m and n being two integers greater than 1, said m-pulse counter being reset by said timing means at the end of each of said intervals with concurrent advance of said shift register by one stage, any stage of said register being loaded with a mark upon said m-pulse counter reaching its counting capacity during the corresponding interval, said high-error-rate signal EPT being generated upon simultaneous presence of marks in all stages of said shift register.

### Claim 9 (depends on 8)

A synchronizing unit as defined in claim 8 wherein said malfunction detector further comprises an AND gate and a NOR gate, each having n inputs respectively connected to all stages of said shift register, and a flip-flop with a setting input connected to an output of said AND gate and with a resetting input connected to an output of said NOR gate.

### Claim 10 (depends on 1, 2, 3, 4)

A synchronizing unit as defined in claim 1, 2, 3 or 4 wherein said malfunction detector further includes a monitoring circuit connected to said decoder and to said timing means for emitting a confirmation signal ATL in response to a certain bit appearing in a predetermined time position of said alignment word B.

### Claim 11 (depends on 10)

A synchronizing unit as defined in claim 10 wherein said monitoring circuit comprises a plurality of cascaded flip-flops with clock inputs connected to said timing means for receiving said second marking pulse TB therefrom, the first of said cascaded flip-flops having a data input connected to an output of said decoder for receiving said certain bit therefrom, and a coincidence gate with inputs connected to respective outputs of said cascaded flip-flops.

### Claim 12 (depends on 11)

A synchronizing unit as defined in claim 11 wherein said coincidence gate has a further input connected to said logic circuitry for blocking the generation of said confirmation signal ATL in the presence of said error signal FAT.

### Claim 13 (depends on 1, 2, 3, 4)

A synchronizing unit as defined in claim 1, 2, 3 or 4 wherein said timing means, said correlation means and said malfunction detector are incorporated in a single integrated-circuit chip.