# US 4,394,657 A · Decoder circuit

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- Number: US 4,394,657 A
- Document ID: US4394657A
- Status: Granted
- Kind: A
- Application number: 06/217,757
- Filed: 1980-12-18
- Granted: 1983-07-19
- Earliest claimed: 1980-12-18
- Assignees: Fujitsu Limited
- Inventors: Hideaki Isogai; Yukio Takahashi
- Web page: https://patentgrep.com/patent/US4394657A

## CPC

- G11C 8/10: Decoders
- G11C 8/00: Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413)
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 11/4116: {with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL}
- G11C 11/415: Address circuits
- H03K 5/15: Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors (distributing, switching or gating arrangements H03K17/00)
- H03K 19/086: Emitter coupled logic
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A decoder circuit comprises input gates, a logic circuit for generating an output according to input signals, an output gate for driving a word line, and a current control device for activating the output gate according to the output of the logic circuit.

## Claims

### Claim 1

A decoder circuit, operatively connectable to receive a plurality input signals "a.sub.0, a.sub.1, a.sub.2, - - - , a.sub.i " and to a word line, comprising:
input gates, operatively connectable to receive the plurality of input signals "a.sub.0, a.sub.1, a.sub.2, - - - , a.sub.i ", for generating inverse signals "a.sub.0, a.sub.1, a.sub.2, - - - , a.sub.i " in dependence upon the plurality of input signals "a.sub.0, a.sub.1, a.sub.2, - - - , a.sub.i ";
a logic circuit, operatively connected to said input gates, for generating an output in dependence upon combined input signals that are the combination signals of said signals a.sub.0 through a.sub.i and a.sub.0 through a.sub.i ;
an output gate, operatively connected to said logic circuit and operatively connectable to the word line, for selectively driving the word line by the output supplied from said logic circuit; and
current control means, electrically connected between a voltage source and said output gate, for switching a current from said voltage source and activating said output gate.

### Claim 2 (depends on 1)

A decoder circuit as claimed in claim 1, wherein said current control means comprises a PNP transistor.

### Claim 3 (depends on 1)

A decoder circuit as claimed in claim 1, wherein said logic circuit comprises a multi-emitter transistor comprising an AND-circuit.

### Claim 4 (depends on 1)

A decoder circuit as claimed in claim 1, wherein said decoder circuit further comprises:
voltage clamping means, operatively connected to said output gate, for clamping an input voltage of said output gate; and
biasing means, electrically connected to said voltage clamping means, for biasing said output gate.

### Claim 5

A decoder circuit for a word line, operatively connectable to receive input bit signals, said decoder circuit comprising:
an input gate, operatively connectable to receive the input bit signals, for generating gate signals and inverted gate signals;
a logic gate, operatively connected to said input gate, for generating a logic signal in dependence upon predetermined ones of the gate signals and the inverted gate signals;
a current switch, operatively connected to said logic gate, for passing current therethrough in dependence upon the logic signal;
current control means, operatively connected to said current switch at a first node, for controlling current flow in dependence upon the current from said current switch; and
a word line driver, operatively connected to said current control means at a second node, for driving the word line.

### Claim 6 (depends on 5)

A decoder circuit as claimed in claim 5, wherein said current control means comprises a transistor operatively connected to said current switch and to said word line driver.

### Claim 7 (depends on 5)

A decoder circuit as claimed in claim 5, further comprising a constant voltage circuit, operatively connected to the first node, for generating a constant voltage.

### Claim 8 (depends on 5)

A decoder circuit as claimed in claim 5, wherein said word line driver has an input, said decoder circuit further comprising:
a parallel circuit operatively connected to the second node; and
a biasing circuit operatively connected to said parallel circuit, so that the input of said word line driver is maintained at a predetermined voltage.

### Claim 9 (depends on 5)

A decoder circuit as claimed in claim 5, wherein said logic gate comprises an AND gate operatively connected to said input gate and to said current switch.

### Claim 10 (depends on 5)

A decoder circuit as claimed in claim 5, wherein said logic gate comprises a multiemitter transistor operatively connected to said input gate and to said current switch.

### Claim 11 (depends on 5)

A decoder circuit as claimed in claim 5, wherein said logic gate comprises a pair of diodes operatively connected between said input gate and said current switch.