Logic circuit including at least one resistor or one transistor having a saturable resistor field effect transistor structure

A logic circuit comprising a first leg wherein a first field-effect transistor is in series with a first saturable resistor interposed on the drain side in the supply of the first tranistor, a second leg comprising a second field-effect transistor in which the supply on the drain side is common with the supply of said first circuit leg, the gate of the second transistor being connected to the drain of the first transistor, the supply circuit of the second transistor being closed across a forward-biased diode and a third transistor which is identical with the first on the ground on the common supply connected to the source of the first transistor, an input terminal connected to a terminal which is common to the gates of the first and third transistors, and an output terminal connected between the diode and the third transistor;

• wherein at least a selected one of said field effect transistors or said saturable resistors has a saturable resistor structure comprising a layer of semiconductor material on a semi-insulating substrate, the character and type of doping of said material being such as to set up a dipolar domain in respect of an electric field which is higher than a so-called critical value, and further comprising two ohmic contacts on said layer, wherein a groove is cut in the semiconductor layer between the ohmic contacts so as to define a residual channel in the material, the dimensions of said groove being such that the critical value of the electric field is overstepped in respect of a value of the order of one volt of the voltage between said ohmic contacts.