# US 4,394,543 A · Telephone line holding circuit

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- Number: US 4,394,543 A
- Document ID: US4394543A
- Status: Granted
- Kind: A
- Application number: 06/270,507
- Filed: 1981-06-04
- Granted: 1983-07-19
- Earliest claimed: 1981-06-04
- Assignees: Lear Siegler, Inc.
- Inventors: Francis P. Keiper, Jr.; John N. Kerns
- Web page: https://patentgrep.com/patent/US4394543A

## CPC

- H04M 3/301: {Circuit arrangements at the subscriber's side of the line}
- H04M: TELEPHONIC COMMUNICATION (circuits for controlling other apparatus via a telephone cable and not involving telephone switching apparatus G08)

## Abstract

A telephone line holding circuit is disclosed which is adapted for temporary connection across a telephone line to maintain that line in a hold condition while line measurements and tests are being performed. The holding circuit is designed to be used over a wide range of line supply voltages and line resistances without introducing line measurement errors. The holding circuit includes a current regulator which maintains the line current at a predetermined level as long as the voltage appearing across the line remains above a predetermined voltage level. The holding circuit also includes a voltage regulator which reduces the predetermined current level to a value which prevents the average line voltage from being reduced below the predetermined voltage level. The holding circuit further includes circuit elements for protecting the circuit elements from damage caused by the application of excessive voltage on the line.

## Claims

### Claim 1

A holding circuit adapted for connection across a telephone line which has a voltage across the line and a current flowing through the line when held, said holding circuit being adapted to maintain the line on hold, said holding circuit comprising:
(a) current regulating means responsive to a current flow through a telephone line having a voltage across the line and a current flowing through the line for maintaining the line current at a predetermined current level when the voltage across the line is at least at a predetermined minimum voltage level;
and
(b) voltage regulating means reponsive to the voltage appearing across the line for preventing an average of the line voltage from being reduced below said predetermined minimum voltage level, said voltage regulating means controlling said current regulating means in response to current flow through the telephone line and the difference between voltage across the telephone line and a reference voltage.

### Claim 2 (depends on 1)

The holding circuit of claim 1 in which the voltage regulating means includes means for reducing the line current below the predetermined current level.

### Claim 3 (depends on 1)

The holding circuit of claim 1 in which the predetermined minimum voltage level is chosen to be greater than the peak amplitude of an AC test signal applied to the line for line test purposes.

### Claim 4 (depends on 3)

The holding circuit of claim 3 in which the voltage regulating means includes means for rendering the voltage regulating means non-responsive to line voltage variations caused by the AC test signal.

### Claim 5 (depends on 1)

The holding circuit of claim 1 in which the current regulating means includes:
a first transistor;
means for connecting the first transistor across the telephone line;
means for sensing the line current; and
first control means for controlling the conduction of the first transistor in response to the means for sensing the line current, whereby the conduction of the first transistor is varied to maintain the line current at the predetermined current level.

### Claim 6 (depends on 5)

The holding circuit of claim 5 in which the voltage regulating means further includes:
(a) means for sensing the line voltage and comparing it to said reference voltage; and
(b) second control means for controlling the conduction of the first transistor in response to the means for sensing the line voltage, whereby the conduction of the first transistor is reduced to prevent the line voltage from being reduced below the predetermined minimum voltage level.

### Claim 7 (depends on 5)

The holding circuit of claim 5 further including current limiting means for blocking the flow of line current through the first transistor whenever the line voltage exceeds a first predetermined maximum voltage level.

### Claim 8 (depends on 5)

The holding circuit of claim 5 further including voltage limiting means for limiting the voltage level across the first transistor whenever the line voltage exceeds a second predetermined maximum voltage level.

### Claim 9 (depends on 5)

The holding circuit of claim 5 in which the first transistor is a field effect transistor having drain, source and gate terminals; the means for connecting the first transistor across the line comprises means for connecting the drain terminal to one side of the line, and means for connecting the source terminal through a first resistance to the other side of the line; and the means for sensing the line current includes the voltage drop appearing across the first resistance.

### Claim 10 (depends on 9)

The holding circuit of claim 9 in which the first control means includes:
means for providing a gate bias voltage to the gate terminal of the field effect transistor to bias it into conduction;
a second transistor having base, emitter, and collector terminals;
means for connecting the second transistor to the gate terminal of the field effect transistor so that conduction of the second transistor reduces the gate bias voltage and conduction of the field effect transistor;
first bias means responsive to the voltage drop across the first resistance; and
means for connecting the first bias means across the base and emitter terminals of the second transistor to bias it into conduction whenever the first bias means exceeds the base-emitter junction voltage of the second transistor.

### Claim 11 (depends on 10)

The holding circuit of claim 10 in which the voltage regulating means includes:
means for sensing a portion of the line voltage and means for comparing it to a reference voltage;
second bias means responsive to the difference between the reference voltage and the sensed portion of the line voltage; and
means for connecting the second bias means across the base and emitter terminals of the second transistor to bias it into conduction whenever the sensed portion of the line voltage is less than the referenced voltage.

### Claim 12 (depends on 9)

The holding circuit of claim 9 further including:
a third transistor;
means for connecting the third transistor in series with the first transistor;
means for biasing the third transistor into conduction; and
means for removing the bias from the third transistor whenever the line voltage exceeds a first predetermined maximum voltage level.

### Claim 13 (depends on 12)

The holding circuit of claim 12 in which the means for removing the bias from the third transistor includes:
a fourth transistor;
means for connecting the fourth transistor to the third transistor so that when the fourth transistor is biased into conduction it shunts the bias to the third transistor;
first and second zener diodes;
means for connecting the first and second zener diodes in series across the drain and source terminals, respectively, of the field effect transistor; and
means for connecting the junction between the first and second zener diodes to the base terminal of the fourth transistor.

### Claim 14 (depends on 11)

The holding circuit of claim 11 in which the second bias means includes:
an operational amplifier having inverting and non-inverting input terminals and an output terminal;
means for connecting the reference voltage to the non-inverting input terminal of the amplifier;
means for connecting the means for sensing a portion of the line voltage to the inverting input terminal of the amplifier; and
means for connecting the output terminal of the amplifier to the base terminal of the second transistor so that output signals from the amplifier appear across the base and emitter terminals of the second transistor.

### Claim 15 (depends on 14)

The holding circuit of claim 14 further including a capacitor, and means for connecting the capacitor between the inverting input terminal and the output terminal of the amplifier to render the amplifier non-responsive to line voltage variations caused by the application of an AC test signal to the line.