# US 4,394,406 A · Double polysilicon contact structure and process

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- Number: US 4,394,406 A
- Document ID: US4394406A
- Status: Granted
- Kind: A
- Application number: 06/164,647
- Filed: 1980-06-30
- Granted: 1983-07-19
- Earliest claimed: 1980-06-30
- Assignees: International Business Machines Corporation
- Inventors: James R Gardiner; Stanley R. Makarewicz; Martin Revitz; Joseph F. Shepard
- Web page: https://patentgrep.com/patent/US4394406A

## CPC

- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10W 20/4451: {Semiconductor materials, e.g. polysilicon}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.

## Claims

### Claim 1

A process for fabricating a contact structure for a semiconductor device including at least two superimposed polysilicon conductors comprising the steps of:
A. forming a first insulating layer 2 (FIG. 3) on a semiconductor substrate A to a preselected thickness, said insulating layer 2 being formed of silicon dioxide and having a thickness in the order of 300 to 700 A,
B. forming a first conductive polysilicon layer 3 (FIG. 3) on the first insulating layer 2, said polysilicon layer 3 having a thickness in the order of 3000 A to 5000 A,
C. forming a first dielectric layer 4 (FIG. 4) on the first conductive polysilicon layer 3, said first dielectric layer 4 being formed of silicon dioxide and having a thickness in the order of 1000 A to 4000 A,
D. patterning the first insulating 2 and dielectric 4 and conductive polysilicon layers 3 into a preselected shape (FIG. 5),
E. patterning a second dielectric layer 5 (FIG. 5) on the first dielectric layer as an etch barrier to selected etchants, said second dielectric layer 5 being selected from the group consisting of silicon nitride and aluminum oxide, said second dielectric layer 5 having a thickness in the order of 200 to 1000 A,
F. forming a second conductive polysilicon layer 7 (FIG. 7) on the second dielectric layer 5 and superimposed, in part at least, on the first conductive polysilicon layer 3, said second polysilicon layer 7 having a thickness in the order of 3000 to 5000 A,
G. forming a third dielectric layer 8 (FIG. 7) on the second conductive polysilicon layer 7, said third dielectric layer 8 being formed of silicon dioxide and having a thickness in the order of 1000 to 2000 A,
H. etching a contact opening 16' (FIG. 9) in the third dielectric 8 to expose the second conductive polysilicon layer 7 overlying the first conductive polysilicon layer 3 whereby the second dielectric layer 5 prevents the etchant from exposing the first conductive polysilicon layer 3 by way of voids existing in the second conductive polysilicon layer 7 due to enlarged polysilicon grains, and
I. forming a metal contact 12' in the opening 16' (FIG. 9), whereby the second dielectric layer 5 prevents the etchant from attacking the first dielectric layer 4 overlying the first conductive polysilicon layer 3 and exposing the surface of the first polysilicon layer 3 to the metal 12 thereby physically joining together the first and second conductive polysilicon layers 3, 7.