# US 4,393,577 A · Semiconductor devices and method of manufacturing the same

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- Number: US 4,393,577 A
- Document ID: US4393577A
- Status: Granted
- Kind: A
- Application number: 06/329,759
- Filed: 1981-12-11
- Granted: 1983-07-19
- Earliest claimed: 1978-10-27
- Assignees: Nippon Telegraph & Telephone Public Corporation
- Inventors: Kazuo Imai
- Web page: https://patentgrep.com/patent/US4393577A

## CPC

- H10P 30/204: {into Group IV semiconductors}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 30/208: {of electrically inactive species}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 90/1906: {Preparing SOI wafers}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P 90/191: {using full isolation by porous oxide silicon [FIPOS]}
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- Y10S 148/084: Ion implantation of compound devices
- Y10S 148/085: Isolated-integrated
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

In a semiconductor device of the type comprising a semiconductor substrate made of P type silicon, a P type monocrystalline silicon region formed on the major surface of the substrate and containing a P type impurity, and a porous silicon oxide region surrounding the P type silicon region, the porous silicon oxide region is made to contact all side surfaces of the P type silicon region and all or at least a portion of the bottom surface thereof.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising the steps of selectively implanting proton ions into a principal surface of a P type monocrystalline silicon substrate;
heating said silicon substrate to form an N type monocrystalline silicon region;
anodizing said substrate to form a porous silicon region extending in a thickness direction from the major surface of said P type monocrystalline substrate except said N type silicon region, said porous silicon region being formed to contact with all side surfaces and at least a portion of a bottom surface of said N type silicon region; and
thermally oxidizing said porous silicon region for converting the same into a porous silicon oxide region while at the same time converting said N type silicon region into a P type silicon region.

### Claim 2 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1 wherein said porous silicon region is formed to contact the entire bottom surface of said N type silicon region.

### Claim 3 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1 wherein said silicon substrate is heated to a temperature of from 300.degree. to 500.degree. C. to form said N type silicon region.

### Claim 4 (depends on 1)

The method of forming a semiconductor device according to claim 1 wherein said silicon substrate is heated to a temperature of from 850.degree. C. to 1100.degree. C. for forming said porous silicon oxide region.

### Claim 5 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1 which further comprises the steps of applying oxidation resistant film on a portion of said monocrystalline silicon substrate where said N type silicon region is to be formed, before implanting said proton ions, and removing said oxidation resistant film after said N type silicon region has been converted into said P type silicon region.

### Claim 6 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1 which further comprises a step of selectively incorporating a group V impurity into said monocrystalline silicon substrate prior to implant said proton ions thereby to form an N type silicon region.

### Claim 7 (depends on 1)

The method of manufacturing a semiconductor device according to claim 1 further comprising a step of selectively incorporating a group V impurity into said P type silicon region thereby forming an N type silicon region.

### Claim 8 (depends on 1)

The method according to claim 1 which further comprises a step of incorporating an N type impurity into said P type silicon region to form source and drain regions thereby forming an N channel type MIS field effect transistor.

### Claim 9 (depends on 5)

The method of manufacturing a semiconductor device according to claim 5 which further comprises a step of incorporating a group V impurity into a region beneath said oxidation resistant film to form an N type silicon region concurrently with the implantation of said proton ions.

### Claim 10 (depends on 5)

The method of manufacturing a semiconductor device according to claim 5 which further comprises a step of selectively incorporating a group V impurity into said P type silicon region to form an N type silicon region.

### Claim 11 (depends on 6)

The method according to claim 6 which further comprises a step of incorporating a P type impurity into said N type silicon region doped with said group V impurity to form source and drain regions thus obtaining a P channel type MIS field effect transistor.