# US 4,393,573 A · Method of manufacturing semiconductor device provided with complementary semiconductor elements

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- Number: US 4,393,573 A
- Document ID: US4393573A
- Status: Granted
- Kind: A
- Application number: 06/181,357
- Filed: 1980-08-26
- Granted: 1983-07-19
- Earliest claimed: 1979-09-17
- Assignees: Nippon Telegraph & Telephone Public Corporation
- Inventors: Kotaro Kato; Tetsuma Sakurai
- Web page: https://patentgrep.com/patent/US4393573A

## CPC

- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10D 84/0121: {the complementary BJTs being vertical BJTs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/673: {Vertical complementary BJTs}
- H10D 84/676: {Combinations of only thyristors}
- H10W 10/019: {using epitaxial passivated integrated circuit [EPIC] processes}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The semiconductor device is provided with semiconductor elements having the complementary characteristics and high breakdown strength. These semiconductor elements are formed in N and P islands respectively each having an inverted frustum shape. Surfaces of the frustum are inclined by an angle determined by semiconductor crystal structure. Side and bottom surfaces of the islands are formed adjacent to an insulating layer and both islands are supported part from the polycrystalline semiconductor layer. All side and bottom surfaces of the islands adjacent the insulating layer are made of high impurity substance of the same type as respective islands.

## Claims

### Claim 1

A method of manufacturing a compound semiconductor device comprising the steps of:
applying a first mask layer onto one major surface of a semiconductor substrate except a first local region, said first mask layer having an upper layer and a lower layer of the same material and an intermediate layer of a different material having a first etching speed;
forming a first semiconductor layer of a first conductivity type on the entire surface of said substrate by an epitaxial growth process, said first semiconductor layer including a single crystalline layer grown from said first local region of said semiconductor substrate, and a polycrystalline layer grown from said first mask layer;
forming a second mask layer of said same material on a portion of said first semiconductor layer corresponding to said first local region, said second mask layer being etchable by a solution which barely etches said intermediate layer and being substantially thicker than said lower layer of said first mask layer;
etching said first semiconductor layer by using said second mask layer so as to leave only said single crystalline layer having inclined surfaces determined by a crystal structure of said single crystalline layer;
removing said second mask layer;
forming a layer containing an impurity of the first conductivity type at a high concentration over the entire outer surface of said single crystalline layer;
forming a first insulating layer on said single crystalline layer;
removing said first mask layer;
forming a second semiconductor layer of a second conductivity type over the entire surface of the substrate by epitaxial growth process, said second semiconductor layer including a polycrystalline layer grown from said first insulating layer and a single crystalline layer grown from said semiconductor substrate;
selectively forming a third mask layer on the single crystalline layer of the second semiconductor layer;
etching said second semiconductor layer by using said third mask layer so as to leave a single crystalline layer of the second semiconductor layer on a second local region of the semiconductor substrate thereby forming inclined surfaces determined by crystal structure of said semiconductor substrate;
removing said third mask layer;
forming a layer containing at a high concentration an impurity of the second conductivity type on the entire outer surface of the remaining single crystalline layer of said second semiconductor layer and exposed surface of said substrate;
forming a second insulating layer on a surface containing the remaining single crystalline layer of said second semiconductor layer and exposed surface of said substrate;
forming a polycrystalline semiconductor layer on said surfaces of said first and second insulating layers;
removing said semiconductor substrate; and
forming semiconductor elements having complementary characteristics in respective exposed single crystalline layers by utilizing a surface formed by polishing as a major plane.

### Claim 2 (depends on 1)

The method according to claim 1 wherein said step of removing said semiconductor substrate includes a step of cutting away the single crystalline layers of the first and second semiconductor layers in parallel with the major plane of said semiconductor substrate.

### Claim 3 (depends on 1, 2)

The method according to claim 1 or 2 wherein said semiconductor substrate comprises silicon.

### Claim 4 (depends on 3)

The method according to claim 3 wherein said intermediate film having said first etching speed of said first film layer comprises a silicon nitride film, and wherein said upper and lower mask layers comprise silicon oxide films.

### Claim 5 (depends on 1, 2)

The method according to claim 1 or 2 wherein each mask layer has a substantially square shape.