# US 4,393,480 A · Address buffer circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,393,480 A - Document ID: US4393480A - Status: Granted - Kind: A - Application number: 06/234,197 - Filed: 1981-02-13 - Granted: 1983-07-12 - Earliest claimed: 1980-02-16 - Assignees: Fujitsu Limited - Inventors: Hiroshi Shimada - Web page: https://patentgrep.com/patent/US4393480A ## CPC - H03K 19/09425: {Multistate logic (H03K19/096 takes precedence)} - G11C 8/00: Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413) - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 11/418: Address circuits - H03K 19/09429: {one of the states being the high impedance or floating state} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An address buffer circuit which generates a pair of complementary signals for selecting a memory cell according to an address input signal is disclosed. This address buffer circuit comprises a short circuit device connected between a pair of output terminals for the complementary signals. During the stand-by period of a memory, the short circuit device electrically connects the pair of output terminals, so that the potential of both of the pair of output terminals becomes an intermediate level between high and low levels provided at the output terminals during the active period of the memory. ## Claims ### Claim 1 An address buffer circuit, having an active period which has high and low levels and having a standby period, which generates a pair of complementary output signals corresponding to an address input signal, comprising: buffer circuit means for buffering the address input signal; means, operatively connected to said buffer circuit means, for suspending power consumption by said address buffer circuit when in the stand-by period responsive to an external signal; output means, operatively connected to said buffer circuit means, having a par of output terminals for outputting said pair of complementary output signals; and short circuit means, operatively connected between said pair of output terminals of said output means, for forcing the potential of said pair of output terminals to a same potential between the high and low levels of said address buffer circuit in the active period by electrically connecting said pair of output terminals in said stand-by period. ### Claim 2 (depends on 1) An address buffer circuit as claimed in claim 1, wherein said external signal comprises a chip select signal. ### Claim 3 (depends on 1) An address buffer circuit as claimed in claim 1, wherein said output means comprises a push-pull circuit operatively connected to said address buffer circuit and said short circuit means. ### Claim 4 (depends on 1) An address buffer circuit as claimed in claim 1, wherein said short circuit means comprises a MOS transistor operatively connected between said pair of output terminals of said output means. ### Claim 5 (depends on 4) An address buffer circuit as claimed in claim 4, wherein said MOS transistor is operatively connected to receive and is controlled by the external signal. ### Claim 6 An address buffer circuit, operatively connectable to receive an external address signal and an external chip select signal and having a stand-by period, comprising: address and buffer means, operatively connectable to receive the external address signal and the external chip select signal, for generating first and second internal address signals at first and second output terminals, respectively, responsive to the external address signal and the external chip select signal; and short circuit means, operatively connected between the first and second output terminals of said address and buffer means and operatively connectable to receive the external chip select signal, for connecting the first and second output terminals together responsive to the external chip select signal, so that the first and second output terminals are held at the same level, the first and second internal address signals are at the same level and power consumption by said address buffer circuit is suspended when in the stand-by period. ### Claim 7 (depends on 6) An address buffer circuit as claimed in claim 6, wherein said short circuit means comprises a transistor operatively connected between the first and second output terminals. ### Claim 8 (depends on 7) An address buffer circuit as claimed in claim 7, wherein said transistor is a MOS transistor. ### Claim 9 (depends on 6) An address buffer circuit as claimed in claim 6, wherein said address and buffer means comprises: first means, operatively connected to said short circuit means and operatively connectable to receive the external chip select signal, for generating first and second internal chip select signals responsive to the external chip select signal; second means, operatively connected to said first means and operatively connectable to receive the external address signal, for generating first and second internal signals responsive to the external address signal and the first internal chip select signal; and a push-pull circuit, operatively connected to said first means, said second means and said short circuit means, for generating the first and second internal address signals responsive to the first and second internal signals and the second internal chip select signal. ### Claim 10 (depends on 9) An address buffer circuit as claimed in claim 9, wherein said first means comprises: a first inverter operatively connectable to receive the external chip select signal; a second inverter, operatively connected to said first inverter and said push-pull circuit, for generating the second internal chip select signal; a third inverter operatively connected to said second inverter; and a fourth inverter, operatively connected to said third inverter and said second means, for generating the first internal chip select signal. ### Claim 11 (depends on 9) An address buffer circuit as claimed in claim 9, wherein said second means comprises: a first inverter operatively connectable to receive the external address signal; a second inverter, operatively connected to said first inverter and said push-pull circuit, for generating the first internal signal; a third inverter, operatively connected to said second inverter and said push-pull circuit, for generating the second internal signal; and first through third power down transistors, operatively connected to said first means and said first through third inverters, respectively, for cutting off power supplied to said first through third inverters responsive to the first internal chip select signal. ### Claim 12 (depends on 9) An address buffer circuit as claimed in claim 9, wherein said address buffer circuit further comprises first and second power down transistors, operatively connected to said first means and said push-pull circuit, for cutting off power supplied to said push-pull circuit responsive to the second internal chip select signal. ### Claim 13 An address buffer circuit operatively connectable to receive an external chip select signal, comprising: address means for generating first and second internal address signals, said address means comprising: a push-pull circuit producing outputs; and a power down transistor operatively connected to said push-pull circuit, operatively connectable to receive the external chip select signal and being controlled by the external chip select signal; and short circuit means, operatively connected to said-push-pull circuit and operatively connectable to receive the external chip select signal, for forcing the outputs of said push-pull circuit to a same potential level and being controlled by the external chip select signal.