US 4,393,468 A · Bit slice microprogrammable processor for signal processing applications

Abstract

A programmable device for signal processing applications in which short loops of digital data are processed repetitively and in parallel. The device consist of five independently programmable subsystems whose functions are able to operate simultaneously. The apparatus is intended for use in a connection with a digital multiplier device and a digital memory device for such signal processing applications as fast Fourier transforms and time domain filtering in real time or near real time. The five parallel functions are 1. to move data in and out of an external memory device between selected registers; 2. to move data in and out of an external multiplier between selected registers and an arithmetic logic unit (ALU); 3. to move data from the output of a multiplier to selected registers and to the ALU; 4. to propagate data selectively through a chain of registers, the chain being of preselectable length; and 5. to perform selected arithmetic and logic operations. The device is provided with an instruction set capable of completely defining any of the five simultaneously allowable functions. The device structure is modular to permit expansion of data word length at the ALU. Internally generated control bit signals are capable of explicitly forcing a carry or inhibiting a carry, thereby to permit independent parallel operation or extended word length operation under program control. The entire apparatus is intended to be embodied as an integrated circuit in a single chip of semiconductor material.

Claims11

Dependent claims

An integrated circuit device for processing digital data in response to instruction signals in connection with a digital memory means and multiplier means, said device comprising:

a plurality of storage registers for storing said data;
an arithmetic logic unit for performing preselectable arithmetic and logic operations on said data in response to said instruction signals;
first means for selectively coupling said digital memory means and preselectable ones of said storage registers for moving data between said memory means and said preselected storage registers in response to said instruction signals;
second means for selectively coupling preselectable ones of said storage registers and said arithmetic logic unit to said multiplier means for moving data from said preselected storage registers and said arithmetic logic unit to said multiplier means in response to said instruction signals;
third means for selectively coupling said multiplier means to preselectable ones of said storage register means and said arithmetic logic unit for moving data from said multiplier means to said preselected storage registers and said arithmetic logic means in response to said instruction signals;
and
fourth means for selectively coupling preselectable ones of said storage registers for moving data through said preselected storage registers in response to said instruction signals,
wherein said first, second, third and fourth selective coupling means and said arithmetic logic unit are simultaneously operable in response to said instruction signals.

5 more elements

An integrated circuit device for processing digital data in response to instruction signals for use in connection with digital memory means for storing data and external multiplier means, said device comprising:

a plurality of storage registers for storing said data, each one of said storage registers having associated therewith a register multiplexer for controlling access thereto from at least one other of said storage registers and at least one other source of data, said plurality of storage registers being interconnected with one another through said associated register multiplexers so that said storage registers are coupled together responsive to said instruction signals in a single register stack, a plurality of parallel independent register stacks, or a loop of registers;
an arithmetic logic unit operative to perform preselectable arithmetic and logic operations on data applied at a first operand input terminal and at a second operand input terminal, said arithmetic logic unit having connected thereto a first operand multiplexer for controlling access to said first operand input terminal and a second operand multiplexer for controlling access to said second operand input terminal, said first operand multiplexer and said second operand multiplexer being connected to the output of each one of said storage registers, and at least one of said operand multiplexers being connected to receive input from said multiplier means;
first output multiplexer means for preselectably multiplexing output data from each one of said storage registers, from said arithmetic logic unit, and from said memory means to said multiplier means;
and
second output multiplexer means for preselectably multiplexing output data from at least two of said storage registers to said memory means,
wherein said storage registers with associated register multiplexers, said arithmetic logic unit with associated operand multiplexers, said first output multiplexer means and said second output multiplexer means are all simultaneously operable in response to said instruction signals for high-speed, parallel operation.

3 more elements

Dependencies are inferred from the claim text.

Bit slice microprogrammable processor for signal processing applications

Life of this patent

Bit slice microprogrammable processor for signal processing applications

Life of this patent

Abstract

Claims11