# US 4,393,391 A · Power MOS transistor with a plurality of longitudinal grooves to increase channel conducting area

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- Number: US 4,393,391 A
- Document ID: US4393391A
- Status: Granted
- Kind: A
- Application number: 06/159,778
- Filed: 1980-06-16
- Granted: 1983-07-12
- Earliest claimed: 1980-06-16
- Assignees: Supertex, Inc.
- Inventors: Richard A. Blanchard
- Web page: https://patentgrep.com/patent/US4393391A

## CPC

- H10D 30/658: {having trench gate electrodes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device providing improved utilization of semiconductor surface area by enhancing the current carrying capability per unit area. The improvement arises from contouring the surface in the conductive channel region of the device so that the current carrying channel is wider than the plane surface that it occupies. This morphology may be achieved by forming troughs having optional rectangular, "U", or "V" shapes; the troughs run parallel to the conductive channel current flow. The improvement is especially useful for MOS and power MOS transistors, and is applicable to DMOS transistors as well as conventional MOS transistors.

## Claims

### Claim 1

A semiconductor device comprising in combination:
a substrate having a substantially plane first major surface;
first and second spaced regions of a first conductivity type formed in said surface;
a third region of a second conductivity type opposite said first conductivity type between said first and said second regions at said surface;
a plurality of spaced groove regions in said major surface, said groove regions being separated by portions of said substrate coplanar with said first major surface, and said grooves extending into each of said first, second, and third regions;
a thin insulating layer over said third region both in said grooves and across surface portions coplanar with said first major surface; and
gate means over said insulating layer for controlling a conductive surface channel between said first and second regions in said grooves and at said first major surface.

### Claim 2 (depends on 1)

The device of claim 1, wherein said third region surrounds only one of said first and said second regions at said surface.

### Claim 3 (depends on 1)

The device of claim 1, wherein said grooves are substantially "V"-shaped in cross-section.

### Claim 4 (depends on 1)

The device of claim 1, wherein said gate means comprises a single electrically conductive member having a plurality of recessed portions extending between said first and second regions.

### Claim 5 (depends on 1)

The device of claim 1, wherein said insulator has substantially the same thickness in said groove means and over said surface portion.