# US 4,393,368 A · Multithreshold A/D converter utilizing error amplifiers

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- Number: US 4,393,368 A
- Document ID: US4393368A
- Status: Granted
- Kind: A
- Application number: 06/150,502
- Filed: 1980-05-16
- Granted: 1983-07-12
- Earliest claimed: 1980-05-16
- Assignees: Motorola, Inc.
- Inventors: Erling E. Rasmussen
- Web page: https://patentgrep.com/patent/US4393368A

## CPC

- H03M 1/16: with scale factor modification, i.e. by changing the amplification between the steps {(H03M1/141 takes precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A multithreshold A/D converter utilizes a plurality of error amplifiers interspersed in a primary quantizing stage for selectively deriving a signal to be quantized in a secondary stage. Because the plurality of error amplifiers is interspersed among comparators normally found in multithreshold A/D converters, each error amplifier need have a dynamic range only sufficient to amplify signals equivalent to the difference between two adjacent voltage reference level steps. Further, by maintaining each of said plurality of error amplifiers active at all times the output signal selected for quantizing in the secondary stage is available at the instant the selection is made.

## Claims

### Claim 1

A multithreshold A/D converter comprising:
a plurality of primary comparison means each for comparing a selected threshold reference voltage level with a given analog input signal level; and
a plurality of error amplifiers each of said error amplifiers coupled to a threshold reference voltage level intermediate those threshold reference levels utilized by adjacent pairs of said plurality of comparison means, a selected one of said error amplifiers outputting a signal differential of said intermediate threshold reference voltage level and said given analog input signal level.

### Claim 2 (depends on 1)

The A/D converter of claim 1 wherein said plurality of error amplifiers each comprise monolithically fabricated integrated circuits whereby each error amplifier is matched with and identical to every other error amplifier in said plurality of error amplifiers.

### Claim 3 (depends on 2)

The A/D converter of claim 2 further comprising a plurality of secondary comparison means each for comparing a third selected threshold reference voltage level with the signal differential output by a selected one of said plurality of error amplifiers.

### Claim 4 (depends on 1, 2)

The A/D converter of claims 1 or 2 wherein each of said plurality of comparison means comprises a comparator having clocked differential outputs said comparators further comprising:
first and second input ports, first and second output ports and first and second clock ports;
means for coupling said first input port of each of said comparators to a source of analog signals; and
means for coupling a respective one of each of said second input ports to a respective, selected threshold voltage reference level.

### Claim 5 (depends on 4)

The A/D converter of claim 4 said comparators further comprising:
a plurality of logic gates; and
means for clocking the outputs of adjacent ones of said comparators through a selected one of said plurality of logic gates such that the second output port of a first of said comparators is coupled to the first output of a second of said comparators through said selected one of said plurality of logic gates.

### Claim 6 (depends on 4)

The A/D converter of claim 4 wherein said comparators further comprise:
replica amplifier means for outputting at said first and second output ports respectively an amplified replica of signals input at said first and second input ports respectively when a clock signal is input to said first clock input port; and
logic level generating means coupled to said output ports for regenerating said replica signals into at least one of a logic ONE and a logic ZERO state at said first and second output ports when a clock signal is input at said second clock input port said logic state being determined by the relative potential difference of the signals input at said first and second input ports.

### Claim 7 (depends on 6)

The A/D converter of claim 6 wherein said means for outputting an amplified replica of said signals is a non-linear, limiting amplifier.

### Claim 8 (depends on 6)

The A/D converter of claim 6 wherein said means for outputting an amplified replica of said signals is a differential amplifier having common mode rejection.

### Claim 9 (depends on 6)

The A/D converter of claim 6 wherein said means for regenerating said signals comprises at least a pair of amplifying devices coupled to said first and second output ports with positive feedback to act regeneratively upon the signals at said output ports when clocked at said second clock input port.

### Claim 10 (depends on 7)

The A/D converter of claim 7 wherein said means for regenerating said signals comprises at least a pair of amplifying devices coupled to said first and second output ports with positive feedback to act regeneratively upon the signals at said output ports when clocked at said second clock input port.

### Claim 11 (depends on 10)

The A/D converter of claim 10 wherein said pair of amplifying devices comprise two transistors connected each with the base of one to the collector of the other to provide positive feedback to said output port signals coupled to the respective bases of said two transistors.

### Claim 12 (depends on 9)

The A/D converter of claim 9 wherein said pair of amplifying devices comprise two transistors connected each with the base of one to the collector of the other to provide positive feedback to said output port signals coupled to the respective bases of said two transistors.

### Claim 13 (depends on 5)

The A/D converter of claim 5 wherein said logic gates comprise AND gates.

### Claim 14 (depends on 5)

The A/D conveter of claim 5 wherein said logic gate comprise OR gates.

### Claim 15 (depends on 5)

The A/D converter of claim 5 wherein said logic gates further comprise means for selecting one of said error amplifiers for outputting said signal differential.

### Claim 16 (depends on 3)

The A/D converter of claim 3 further comprising means for selecting said one of said error amplifiers outputting a signal differential of said intermediate threshold reference voltage level and said given analog input signal level.

### Claim 17 (depends on 16)

The A/D converter of claim 16 wherein said means for selecting said one of said error amplifiers comprises output direction means for selectively directing the individual outputs of said error amplifiers to at least one of a first signal sink and a second signal sink.

### Claim 18 (depends on 17)

The A/D converter of claim 17 wherein said first signal sink comprises said plurality of secondary comparison means.

### Claim 19 (depends on 17)

The A/D converter of claim 17 wherein said second signal sink comprises a ground reference.

### Claim 20 (depends on 17)

The A/D converter of claim 17 wherein said output direction means comprises switch means for selectively switching the individual outputs of said error amplifiers to at least one of said first signal sink and said second signal sink said error amplifiers remaining active to provide output to the selected sink at the instant said switch means are selectively switched.