Cached multiprocessor system with pipeline timing

A data processing system that provides for the transfer of information among devices in the data processing system wherein the devices issue commands which include data signals and control information, the control information including code signals that specify the type of information transfer operation that is to be performed, device identification signals that identify the device involved in the transfer of information, and address signals that specify a location in the device to which or from which the information is to be transferred, said data processing system comprising:

• A. random access memory means (28) for storing information in a plurality of addressable storage locations therein,
• B. common control means (10) including
• i. pipeline resource means comprising a control section (FIG. 8A) and a data section (FIG. 8B) for processing commands in an ordered pipeline sequence, said resource means comprising
• a. control input means (352) in the control section for receiving control information and data input means (306) in the data section for receiving data signals,
• b. associative memory means (20) that includes data store means (20B) having addressable storage locations for storing copies of information contained in said random access memory means, and address tag store means (20A) for storing memory addresses that specify the addressable storage locations in said random access memory means that are associated with the information contained in said data store means,
• c. tag compare means (162) for determining whether memory data requested by a command is resident in said associative memory means,
• d. queuing means (176) for receiving commands that seek to access said random access memory means, and
• e. control output means (163) in the control section for transmitting control information therefrom and data output means (163) in the data section for transmitting data signals therefrom,
• ii. memory interface means interconnecting the random access memory means and the common control means comprising
• a. command receiving means (196) for receiving commands that read or write information in said random access memory means,
• b. memory return means (65) for storing information that is read from or written into said random access memory means, and
• c. memory control means (208) connected to said command receiving means and said memory return means for controlling the transfer of information among said random access memory means (184), said command receiving means, and said memory return means (65), and
• iii. timing and control means (26) for controlling the operation of said common control means comprising
• a. pipeline timing means for sequencing commands through successive stages of said pipeline resource means and being further responsive to said tag compare means for enabling a transfer of data requested by a command from said associative memory means to said control output means when data requested by said command is resident in the associative memory means, and
• b. queuing control means (158) responsive to said tag compare means for entering a command in said queuing means (176) when data requested by said command is not resident in said associative memory means, said queuing control means being further responsive to the control information in said command for entering it in said queuing means (176) when the command seeks to write information in said random access memory means.