Method for controlling the clock phase of a receiving system for digital data, phase recovery circuit for effectuating this method and digital data receiving system comprising said circuit
AssigneeU.S. Philips Corporation
InventorDenis Rouffet
Life of this patent
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Abstract
Method for controlling the phase of a decision circuit clock of a receiving system for digital data, according to which the frequencies above 1/T (T=data symbol period) are substantially eliminated, whereafter the phase deviation to be corrected is evaluated and the clock is shifted in accordance with this phase deviation, inclusive of its sign. An example of a circuit for using this method includes a lowpass filter circuit and an evaluation and phase shifting circuit for fixing the optimum decision instants of the decision circuit provided at the output of an adaptive filter.
Claims5
In a receiving system for digital data having a symbol period T and being transmitted after linear modulation over a time-varying channel with limited passband, said system comprising a filter circuit for the output signal of the channel and a subsequent decision circuit for effectuating an estimation and a reconstruction of each of the tramsmitted digital data at the input of the channel on the basis of the output signal of the filter circuit and in the rhythm of a clock which is associated with this decision circuit and whose frequency and phase are determined by a clock recovery circuit permitting a decision which minimizes the error rate, a method for controlling the phase of said clock of the decision circuit, characterized in that the method comprises the following steps:
- imposing on the filter circuit a transfer function such that this circuit substantially eliminates the frequencies above 1/T from the received frequency spectrum and the average energy E of its output signal as a function of the time t and of the symbol period T of the transmitted data at the input of the channel is only defined by an expression of the type E=A+B cos (.pi.t/T), A and B being two constant or slowly varying positive real coefficients;
- estimating the phase deviation .phi..sub.E between the value .phi..sub.M =2.pi.t.sub.M /T maximizing the expression for E and the value .phi.=2.pi.t/T corresponding to the value of the average energy of the output signal of the filter circuit at a sampling instant t preceding the clock phase control;
- shifting the sampling instants fixed by the clock over time t.sub.E =(.phi.-.phi..sub.M)T/(2.pi.), taking its sign into consideration.
A phase recovery circuit for a receiving system for digital data having a symbol period T and being transmitted after linear modulation over a time-varying channel with limited pass-band, characterized in that the phase recovery circuit comprises:
- a lowpass filter circuit having a transfer function such that this circuit substantially eliminates the frequencies above 1/T from the received frequency spectrum and the average energy of its output signal, as a function of the time t and the symbol period T of the transmitted data at the input of the channel, is only defined by an expression of the type E=A+B.multidot.cos (2.pi.t/T), A and B being two constant or slowly varying positive real coefficients;
- an evaluation circuit for determining the phase deviation .phi..sub.E between the value .phi..sub.M =2.pi.t.sub.M /T maximizing the expression for E and the value .phi.=2 .pi.t/T corresponding to the value of the average energy of the output signal of the filter circuit at a sampling instant t preceding the clock phase control;
- and
- a phase shifting circuit for shifting the sampling instants fixed by the clock over a time t.sub.E =(.phi.-.phi..sub.M)T/(2.pi.), taking its sign into consideration.
Dependencies are inferred from the claim text.