US 4,385,382 AGranted

Communication multiplexer having a variable priority scheme using a read only memory

AssigneeHoneywell Information Systems Inc.

InventorsGary J. Goss, Angelo D. Kachemov

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Abstract

A data processing system includes a number of input/output devices coupled to a communication multiplexer which polls the devices in a predetermined order. Apparatus in the communication controller rearranges the polling order to provide highest priority to an input/output device in a receive mode that is currently operative and to give lowest priority to an input/output device in a transmit mode that has just completed its operation.

Claims8

Dependent claims

A data processing system for transferring data bytes comprising:

a system bus;
a main memory coupled to said system bus for storing said data bytes;
a communication multiplexer coupled to said system bus for transferring said data bytes between said main memory and a plurality of communication lines, each of said plurality of communication lines being operative as a receive channel or as a transmit channel;
said communication multiplexer including polling means for sending a sequence of receive channel numbers and transmit channel numbers representative of said receive channel and said transmit channel respectively to said each of said plurality of communication lines and receiving a request signal if one of said plurality of communication lines requests the transfer of said data bytes by responding to a selected one of said sequence of receive channel numbers or transmit channel numbers;
said polling means including:
first counter means responsive to a plurality of output signals for generating a plurality of mode signals indicative of a plurality of modes of operation;
ROM means coupled to said first counter means and responsive to said plurality of mode signals and a plurality of control signals for generating said plurality of output signals;
second counter means coupled to said ROM means and responsive to said plurality of output signals for identifying the last of said sequence of receive channel numbers and the last of said sequence of transmit channel numbers of said sequence;
wherein said plurality of modes of operation includes:
a first mode for generating a first of said sequence of receive and transmit channel numbers;
a second mode for polling each of said receive channels and each of said transmit channels and being responsive to said request signal for implementing the transfer of one of said data bytes;
a third mode for generating a second of said sequence of receive and transmit channel numbers;
and
a fourth mode for testing if a timeout error resulted after an indication that the transfer of data is completed and generating signals indicative of said second mode of operation.

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Dependencies are inferred from the claim text.

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Abstract

A data processing system for transferring data bytes comprising:

a system bus;
a main memory coupled to said system bus for storing said data bytes;
a communication multiplexer coupled to said system bus for transferring said data bytes between said main memory and a plurality of communication lines, each of said plurality of communication lines being operative as a receive channel or as a transmit channel;
said communication multiplexer including polling means for sending a sequence of receive channel numbers and transmit channel numbers representative of said receive channel and said transmit channel respectively to said each of said plurality of communication lines and receiving a request signal if one of said plurality of communication lines requests the transfer of said data bytes by responding to a selected one of said sequence of receive channel numbers or transmit channel numbers;
said polling means including:
first counter means responsive to a plurality of output signals for generating a plurality of mode signals indicative of a plurality of modes of operation;
ROM means coupled to said first counter means and responsive to said plurality of mode signals and a plurality of control signals for generating said plurality of output signals;
second counter means coupled to said ROM means and responsive to said plurality of output signals for identifying the last of said sequence of receive channel numbers and the last of said sequence of transmit channel numbers of said sequence;
wherein said plurality of modes of operation includes:
a first mode for generating a first of said sequence of receive and transmit channel numbers;
a second mode for polling each of said receive channels and each of said transmit channels and being responsive to said request signal for implementing the transfer of one of said data bytes;
a third mode for generating a second of said sequence of receive and transmit channel numbers;
and
a fourth mode for testing if a timeout error resulted after an indication that the transfer of data is completed and generating signals indicative of said second mode of operation.

11 more elements