# US 4,384,353 A · Method and means for internal error check in a digital memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 4,384,353 A
- Document ID: US4384353A
- Status: Granted
- Kind: A
- Application number: 06/235,803
- Filed: 1981-02-19
- Granted: 1983-05-17
- Earliest claimed: 1981-02-19
- Assignees: Fairchild Camera and Instrument Corporation
- Inventors: Ramesh C. Varshney
- Web page: https://patentgrep.com/patent/US4384353A

## CPC

- G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)}
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor digital memory such as a charge coupled device is provided with error detection capability. Error logic responsive to a group of data on the input bus generates a first error code which is stored in memory along with the group of data. When the data is retrieved from memory similar error logic generates a second error code. The first and second error codes are compared, and if the codes are identical the data is assumed to be correct. If codes differ then the data is discarded or errors therein are identified and corrected.

## Claims

### Claim 1

An error detection apparatus responsive to an ED signal, an ED' signal, data and an external error check code received from an external source, with means for coupling said apparatus to a memory having a storing cycle and a reading cycle and an output buffer, comprising:
means, responsive to said ED signal, said ED' signal, said data and said external error check code for generating a first internal error check code and storing said data and said external error check code in said memory during said storing cycle and for generating a second internal error check code and reading said data and said external error check code from said memory to said output buffer during said reading cycle when both said ED signal and said ED' signal are low; and
means, including comparing means, responsive to said ED signal, said ED' signal, said external error check code, said first internal error check code and, said second internal error check code for:
(a) storing said first internal error check code in said memory during said storing cycle and comparing said first internal error check code stored in said memory and said second internal error check code and reading the results of said comparison to said output buffer during said reading cycle when said ED signal is high and said ED' signal is low; and
(b) storing said external error check in said memory during said storing cycle and comparing said external error check code stored in said memory and an external error check code received from said external source and reading the results of said comparison to said output buffer during said reading cycle when both said ED and said ED' signals are high.

### Claim 2 (depends on 1)

An apparatus according to claim 1 wherein said means comprises logic means.

### Claim 3 (depends on 2)

An apparatus according to claim 2 wherein said logic means are embodied in an integrated circuit means.