High density electrically erasable floating gate dual-injection programmable memory device

An electrically erasable floating gate type semiconductor memory array comprising:

• a plurality of field-effect transistor devices each having a source, a drain, a floating gate, and a control gate, the floating gate being isolated from the channel between source and drain by thin insulator and the control gate being isolated from the floating gate by thin insulator, the transistor devices being arranged in array of rows and columns, with the columns of transistor devices being the sources and drains connected to elongated parallel column lines;
• means connecting the control gates of all devices in each row together to provide row lines;
• said memory array functioning to read out logic-level voltage by selective application of logic-level voltage on the column lines and row lines;
• and erasing means comprising:
• means for applying an erase voltage to a selected one of the column lines;
• means for applying a high voltage to all said row lines except a selected row line;
• and means for applying a low voltage to said selected row line;
• said erase voltage and said high voltage being higher than said logic-level voltage, and said low voltage being lower than said high voltage.

An electrically erasable, electrically programmable semiconductor memory device comprising:

• an array of rows and columns of memory cells, each cell having a control gate connected by a row line to control gates of all cells in a row, each cell having a source-drain path connected to its ends to adjacent column lines, a floating gate between said source-drain path and control gate in each cell;
• the memory device functioning to read out logic-level voltage from the memory cells by selective application of logic-level voltage to the row and column lines;
• means for charging the capacitance of a selected one of the column lines to an erase voltage greater than said logic-level voltage over a time interval;
• means for maintaining the control gates of all cells in the array at a high level voltage greater than said logic-level voltage causing the source-drain paths to be in a non-erase condition during said time interval;
• and means for connecting a selected one of said row lines to a lower voltage at a time beginning after said time interval to cause discharging of the floating gate of one of the cells by carrier injection;
• said lower voltage being substantially less than said high level voltage.