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US 4,384,347 AGranted
Semiconductor memory device
AssigneeFujitsu Limited
InventorTomio Nakano
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprising a plurality of memory blocks each including a sense amplifier array and a pair of memory cell groups disposed on both sides of the sense amplifier array, a row decoder for selecting a row line in the plurality of memory blocks, pairs of bus lines, each pair corresponding to one of the sense amplifier arrays and, a column decoder. The column decoder is provided commonly to the plurality of memory blocks and selectively connects a pair of input/output terminals of a sense amplifier of the sense amplifier array in each of the memory blocks to a corresponding one of the pairs of bus lines.
Claims20
A semiconductor memory device comprising:
- a plurality of memory blocks each including:
- a row line;
- and
- a sense amplifier array comprising digit lines, and a plurality of sense amplifiers, operatively connected to said digit lines, each having a pair of input/output terminals;
- and
- a pair of memory cell groups each comprising a plurality of dynamic type memory cells which are selectively connected to said sense amplifier array through said digit lines;
- a row decoder, operativelyy connected to each row line of said plurality of memory blocks, for selecting one of the row lines in said plurality of memory blocks;
- pairs of bus lines, each pair corresponding to one of said sense amplifier arrays and each pair operatively connectable to corresponding pairs of said input/output terminals;
- column lines operatively connected to said pairs of bus lines;
- and
- a column decoder, operatively connected to said column lines, which is common to said plurality of memory blocks and which selectively connects one pair of input/output terminals of said sense amplifiers in each of said memory blocks to a corresponding one of said pairs of bus lines by changing the potential of one of said column lines connected between said column decoder and said plurality of memory blocks.
8 more elements
A semiconductor memory device comprising:
- a plurality of memory blocks each including:
- a row line;
- a sense amplifier array comprising a plurality of sense amplifiers and digit lines operatively connected to said sense amplifiers;
- and
- a pair of memory cell groups each comprising a plurality of dynamic type memory cells which are operatively connected to said sense amplifier aray through said digit lines and each of said memory cells comprising a capacitor operatively connected to ground and a MOS transistor operatively connected to said capacitor, one of said digit lines and one of said row lines, one of the electrodes of said capacitor being formed as a first conductive layer, and the gate electrode of said MOS transistor being formed as a second conductive layer;
- a row decoder, operatively connected to each row line of said plurality of memory blocks, for selecting one of said row lines in said plurality of memory blocks;
- pairs of bus lines, each pair corresponding to one of said sense amplifier arrays and each pair operatively connectable to a corresponding one of said sense amplifiers arrays;
- column lines operatively connected to said plurality of memory blocks and said pairs of bus lines;
- a column decoder, operatively connected to said column lines, which is common to said plurality of memory blocks and which selectively connects one pair of input/output terminals of said sense amplifiers in each of said memory blocks to a corresponding one of said pairs of bus lines by changing the potential of one of said column lines connected between said column decoder and said plurality of memory blocks, said digit lines being formed as a third conductive layer having a first electrical conductivity disposed on said first conductive layer and an insulation layer formed therebetween, said column lines also being formed as said third conductive layer having a first electrical conductivity, and said row lines being formed as a fourth layer having a second electrical conductivity disposed on said third conductive layer and having another insulation layer formed therebetween.
6 more elements
Dependencies are inferred from the claim text.