Back to results
US 4,384,345 AGranted
Read-only memory device
AssigneeFujitsu Limited
InventorKoichi Mikome
Life of this patent
Estimating the term…
Abstract
A read-only memory device comprising first and second memory cell areas is disclosed. In the first memory cell area, the presence or absence of a transistor represents the binary data "0" or "1", while, in the second memory cell area, the presence or absence of a connection for connecting a transistor to one of bit lines represents the binary data "0" or "1".
Claims9
A read-only memory device, for storing binary data having first and second level signals, comprising:
- first and second power supplies;
- a plurality of first word lines;
- a plurality of second word lines;
- a plurality of bit lines crossed with said first word lines and said second word lines and operatively connected to said first power supply;
- a first memory cell area comprising first memory cells at intersections between said first word lines and said bit lines, each first memory cell having a first transistor in dependence upon the first and second level signals of the binary data, each first memory cell present being operatively connected between a respective one of said first word lines and said bit line and to said second power supply, wherein the presence or absence of said first transistor represents a one of the first or second level signals of said binary data, respectively;
- and
- a second memory cell area comprising second memory cells at intersections between said second word lines and said bit lines, each second memory cell having a second transistor operatively connected to a respective one of said second word lines and to said second power supply, wherein the presence or absence of a connection for connecting said second transistor to one of said bit lines represents a one of the first or second level signals of the binary data, respectively.
4 more elements
A read only memory device for storing predetermined binary data having first and second signals, comprising:
- first and second word lines;
- a bit line crossing said first and second word lines;
- a first memory cell area positioned at the intersection of said first word line and said bit line, including:
- a first transistor, operatively connected between said first word line and said bit line, having first a threshold value in dependence upon the first signal;
- and
- a second transistor, operatively connected between said word line and said bit line, having a second threshold value in dependence upon the second signal;
- and
- a second memory cell area positioned at the intersection of said second word line and said bit line, including:
- a third transistor operatively connected to said second word line and operatively connected to said bit line in dependence upon the first signal;
- and
- a fourth transistor operatively connected to said second word line and operatively connected to said bit line in dependence upon the second signal.
8 more elements
Dependencies are inferred from the claim text.