Data processor having apparatus for controlling the selection of decimal digits of an operand when executing decimal arithmetic instructions

A commercial instruction processor coupled to a main memory for executing decimal arithmetic instructions, receiving an operation code, a plurality of descriptor words and a plurality of operands including packed decimal operands and string decimal operands from said main memory and having apparatus for generating decimal digit position signals indicating the decimal digit position to be selected for processing comprising:

• control store means responsive to said operation code for generating a plurality of control store signals;
• multiplexer means coupled to said control store and responsive to said plurality of control store signals and one of said plurality of descriptor words for generating a type signal and said decimal digit position signals;
• register means coupled to said multiplexer means for storing said type signal and said decimal digit position signals indicating a first predetermined decimal digit position;
• and
• read only memory means coupled to said control means and said register means, and responsive to said plurality of control signals, said type signal and said decimal digit position signals representative of said first predetermined digit position for generating said decimal digit position signals indicative of a second predetermined decimal digit position.