Memory security circuit using the simultaneous occurance of two signals to enable the memory
AssigneeNCR Corporation
InventorRathindra N. Devchoudhury
Life of this patent
Estimating the term…
Abstract
A control circuit to disable the operation of a semiconductor microprocessor memory device in event of an unauthorized attempt to access the memory. The memory device is disabled from operation upon removal of the device from the microprocessor. A delayed signal generated outside the memory device enables the control circuit to generate a memory enabling signal. Logic circuit means including a counter generates a signal for a preselected time period during which the delayed signal is required to be generated. Both signals control the enabling of the memory device.
Claims14
A system for controlling the operation of a memory device comprising;
- a memory device (34);
- means (27) for generating a first memory operating signal (V.sub.cc) at the start of operation of said memory device;
- first circuit means (20) coupled to said operating signal generating means for generating a delayed signal (SEC) representing said first memory operating signal delayed a first predetermined time period;
- first logic means (86, 98) responsive to the generation of said first memory operating signal for generating a first control signal (100) for a second predetermined time period;
- and second logic means (88, 108, 90) coupled to said memory device and responsive to the simultaneous occurrence of said delayed signal and said first control signal for generating a second memory operating signal (113) thereby enabling said memory device to be operated.
In a system including an electronic memory unit and a microprocessor to control the reading of or writing of data into said memory unit, a circuit for controlling the operation of the memory unit comprising:
- means for generating a memory energizing signal;
- first circuit means coupled to said electronic memory unit and said energizing signal generating means for delaying the transmission of said energizing signal to said memory unit a first predetermined time period;
- first logic means located within said memory unit coupled to said memory energizing signal generating means for generating a first control signal for a second predetermined time period in response to receiving said memory energizing signal;
- second logic means coupled to said first circuit means for outputting a pulse upon receiving said delayed memory energizing signal;
- and a first bistable logic device located within said memory unit coupled to said first and second logic means for outputting a second memory energizing signal in response to the simultaneous occurrence of said pulse and said first control signal whereby said memory unit is conditioned for operation.
A method for enabling the operation of a memory device comprising the steps of;
- generating a first memory energizing signal at the start of the operation of the memory device;
- generating a first control signal for a first predetermined time period in response to the generation of said first memory energizing signal;
- delaying said first memory energizing signal for a second predetermined time period;
- and generating a second memory energizing signal in response to the simultaneous occurrence of said first control signal and said delayed first memory energizing signal whereby said memory device is enabled.
A method for enabling the operation of a memory device comprising the steps of;
- generating a first memory enabling signal at the start of the operation of the memory device;
- locating a signal delay circuit external to the memory device;
- transmitting the first memory enabling signal to said signal delay circuit;
- generating a delayed memory enabling signal in response to the generation of said first memory enabling signal;
- generating a first control signal for a first predetermined time period in response to the generation of said first memory enabling signal;
- generating a second memory enabling signal in response to the simultaneous occurrence of said first control signal and said delayed memory enabling signal;
- and transmitting said second memory enabling signal to the memory device.
Dependencies are inferred from the claim text.