Shaft angle encoder having a circuit for synthesizing a skipped track output signal

A shaft angle encoder, comprising a rotatable code member having a multiplicity of code tracks including Gray reflected binary tracks ranging in order from zero to n minus 2 and a sine wave track of the order n but omitting a skipped track having the order of n minus 1,

• the track of zero order having the largest divisions while the track of the order n has the finest divisions,
• transducer means for reading said code tracks and for producing binary electrical signals corresponding with said binary tracks and sine wave electrical signals corresponding with said sine wave track,
• a parity detector having inputs for receiving the binary electrical signals corresponding to the binary tracks having the orders of zero through n minus 2 and for producing a corresponding even/odd output indicating whether said binary signals are even or odd,
• a digitizer for digitizing the sine wave signals corresponding to the sine wave track of the order n and thereby producing corresponding digitized binary signals of the order n,
• and an exclusive OR logic device having inputs for receiving the digitized binary signals of the order n and the even/odd output of said parity detector,
• said exclusive OR logic device producing an output which synthesizes the binary electrical output signals corresponding to the skipped track of the order n minus 1.

A circuit for synthesizing skipped track signals in a shaft angle encoder having a multiplicity of code tracks including Gray reflected binary tracks ranging in order from zero to n minus 2 and a sine wave track of the order n but omitting a skipped track having the order of n minus 1, the encoder having transducer means for reading the tracks and for producing binary electrical signals corresponding with the binary tracks and sine wave signals corresponding with the sine track, said circuit comprising

• a parity detector having inputs for receiving the binary electrical signals corresponding to the binary tracks having the orders of zero through n minus 2 and for producing a corresponding even/odd output indicating whether said binary signals are even or odd,
• a digitizer for digitizing the sine wave signals from the sine track of the order n and thereby producing corresponding digitized binary signals of the order n,
• and an exclusive OR logic device having inputs for receiving the digitized binary signals of the order n and the even/odd output of said parity detector,
• said exclusive OR logic device producing an output which synthesizes the binary electrical output signals corresponding to the skipped track of the order n minus 1.