Circular access linkage loop configuration for system communication
AssigneeBurroughs Corporation
InventorRichard K. W. Tam
Life of this patent
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AssigneeBurroughs Corporation
InventorRichard K. W. Tam
Estimating the term…
A plurality of CML integrated circuit chips with input and output gates connected in a circular access linkage loop output-to-input with each chip having an interface mechanism comprising an interface register and a bypass arrangement between the input gate and the output gate so that information may flow from a transmitter output gate to a receiver input gate uni-directionally, (clockwise or counter-clockwise) through the loop by means of the bypass with minimal delay. Utilizing this circular access linkage loop together with a junction box, a number of access loops can be joined together to increase the number of chips which can be linked together. Also disclosed is a multiplexing scheme utilizing the circular access linkage loop for increasing the gate per pin ratio and for higher speed communication between chips.
A current mode logic system of the type including a plurality of sequential logic modules which communicate to one another;
Dependencies are inferred from the claim text.