Demultiplex receiver apparatus
AssigneeBell Telephone Laboratories, Incorporated
InventorCecil W. Farrow
Life of this patent
Estimating the term…
Abstract
Accurate recovery of constituent data streams from a multiplexed serial data stream in which each symbol includes a nonintegral number of frames is accomplished by combining a coherently detected timing signal, which is a component of the received serial data stream, together with a bit clock signal and a symbol clock signal to locate a predetermined bit position within each frame. When the location of the predetermined bit position is determined, frame synchronization is complete and the constituent data streams are correctly demultiplexed from the multiplexed serial data stream. The timing signal has a pulse rate equal to the greatest common divisor of the frame and symbol rates.
Claims7
Receiver apparatus of the type including means (102) responsive to an input signal (RS) for generating a corresponding serial bit stream (SDS) having a plurality of bits arranged in consecutive symbols and also for generating a symbol clock signal (SC) having a first pulse rate related to a rate of occurrence for each symbol and a bit clock signal (BC) having a second pulse rate related to a rate of occurrence for each bit in the corresponding serial bit stream, the serial bit stream also capable of being partitioned into consecutive frames, the receiver apparatus characterized by,
- means (120) responsive to the bit clock signal for generating at least one frame clock signal (e.g., FC1, FC2, FC3, FC4) having a third pulse rate related to a rate of occurrence of consecutive frame, in the corresponding serial bit stream, wherein M/N is a nonintegral rational number,
- means (104, 105) responsive to the input signal for generating a timing signal (TS) having a pulse rate related in a prescribed manner to the first and third pulse rates, and
- means (103, 110, 121) jointly responsive to the symbol clock signal and the timing signal for controlling the at least one frame clock signal to have a phase synchronized with a predetermined bit position (A.sub.0, A.sub.1, A.sub.2, A.sub.3) of each frame, so that a predetermined transition of the frame clock signal occurs at the predetermined bit position of each frame in the corresponding serial bit stream.
Dependencies are inferred from the claim text.