Digital conference time slot interchanger

A time slot interchanger operative for transferring signals between time slots of a first bus and time slots of a second bus, said time slot interchanger comprising

• first and second memories each having storage locations therein, each said storage location corresponding to a particular one of said second bus time slots, the total number of said locations in each memory being equal to the number of second bus time slots,
• a clock having sequential outputs identical and synchronized with the time slots of said first bus,
• means for storing first bus time slot identities in said first memory at storage locations corresponding to the desired second bus time slot transfer,
• said first memory arranged to provide response signals to matches between said clock outputs and time slot identities of said first bus stored in said first memory, each said response signal having a specific locational identity with a particular one of said second bus time slots as determined by the physical location of said stored first bus time slot identity
• means controlled by each said response signal for storing the first bus time slot signal corresponding to the written identity of said matched time slot in said second memory at said specific location associated with said particular one of said second bus time slots, and
• means for transferring said stored signals from said second memory to said output bus.

A communication system arranged for controlling communication signals between a plurality of stations, said system arranged for digital transmission of signal samples between stations, said stations being grouped into clusters, each cluster served by a local control circuit,

• a first signal sample bus for interconnecting said clusters and a second signal sample bus for interconnecting the stations served by each said control circuit, each said bus having established thereon repetitive synchronized frames, each frame having a plurality of time slots with the number of time slots of said first bus being greater in number than the number of time slots of said second bus,
• first and second memories each having storage locations therein, each said storage location corresponding to a particular one of said second bus time slots, the total number of said locations in each memory being equal to the number of second bus time slots,
• a clock having sequential outputs identical and synchronized with the time slots of said first bus,
• means for storing first bus time slot identities in said first memory at storage locations corresponding to the desired second bus time slot transfer
• said first memory arranged to provide response signals to matches between said clock outputs and time slot identities of said first bus stored in said first memory, each said response signal having a specific locational identity with a particular one of said second bus time slots as determined by the physical location of said stored first bus time slot identity
• means controlled by each said response signal for storing the first bus time slot signal corresponding to the written identity of said matched time slot into said second memory at said specific location associated with said particular one of said second bus time slot, and
• means for transferring said stored signals from said second memory to said output bus.