Logic having inhibit mean preventing erroneous operation circuit
AssigneeNippon Electric Co., Ltd.
InventorNoboru Kiyozuka
Life of this patent
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Abstract
A logic circuit operable without erroneous operation is disclosed. The logic circuit comprises a first and a second switching transistor operating in response to the same signal, a first logic gate including an input transistor receiving a signal derived from the first switching transistor and a second logic gate receiving a signal derived from the second switching signal, in which the signal derived from the first switching transistor is independently fed to the first logic gate.
Claims9
A logic circuit comprising a current source, first and second transistors, emitters of said first and second transistors being coupled to said current source in common, first means for operatively supplying a base of said first transistor with a reference voltage, a value of said reference voltage making said first transistor conductive, second means coupled to a collector of said second transistor and responsive to a conducting state of said second transistor for inhibiting said first means from supplying said reference voltage thereby to make said first transistor non-conducting, a third transistor having an emitter coupled to the emitter of said second transistor and a base coupled to the base of said second transistor, third means for applying an input signal to the bases of said second and third transistors in common, a first logic circuit coupled to a collector of said third transistor and controlled by the conducting state of said third transistor, and a second logic circuit coupled to a collector of said first transistor and controlled by the conducting state of said first transistor.
A logic circuit further comprising an input terminal, a first output terminal, a second output terminal, a first switching transistor, a second switching transistor, means coupled to said input terminal for applying an input logic signal to bases of said first and second switching transistors in common, an emitter of said first switching transistor being coupled to an emitter of said second switching transistor, a first logic gate having a first input and coupled to a collector of said first switching transistor and a first output end connected to said first output terminal, said first logic gate including an input transistor having a base connected to said first input end and controlled by said first switching transistor, and a second logic gate having a second input end coupled to a collector of said second switching transistor and a second output end connected to said second output terminal, said second logic gate being independent from the output of said first logic gate at said first output end and controlled by said second switching transistor.
Dependencies are inferred from the claim text.