US 4,382,194 AGranted

Boosting circuit

AssigneeFujitsu Limited

InventorsMasao Nakano, Fumio Baba, Hirohiko Mochizuki

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Abstract

A boosting circuit boosts a voltage of a load capacitor which is charged by a specific voltage. The boosting circuit comprises a boosting capacitor one end of which is connected to receive a clock signal, a charging circuit for charging the boosting capacitor, a gate circuit provided between the load capacitor and the other end of the boosting capacitor, and a gate control circuit for opening the gate circuit upon discharging of the charge of the boosting, that is controlled by the clock signal, to the load capacitor and for closing the gate circuit during discharging of the load capacitor. The charging circuit is provided separately from a circuit for supplying the specific voltage. The charges of the boosting capacitor under the control of the clock signal flow through the gate circuit to the load capacitor.

Claims19

Dependent claims

A boosting circuit, operatively connectable to receive a clock signal .phi. and including a circuit for generating a specific voltage, for boosting a voltage of a load capacitance which is charged to the specific voltage, said boosting circuit comprising:

a boosting capacitance, one end of which is operatively connectable to receive the clock signal .phi.;
a charging circuit, operatively connected to the other end of said boosting capacitance, for charging said boosting capacitance, said charging circuit being provided separately from the circuit for generating the specific voltage;
a gate circuit, operatively connected between the load capacitance and the other end of said boosting capacitance, for transferring the charges held by said boosting capacitance to the load capacitance;
and
a gate control circuit, operatively connected to said gate circuit and said boosting capacitance, and operatively connectable to receive the clock signal .phi., for opening said gate circuit after the transfer of the charge of said boosting capacitance to the load capacitance in dependence upon the clock signal .phi. and for closing said gate circuit during the transfer of the charge of said boosting capacitance to the load capacitance by said gate circuit.

2 more elements

A boosting circuit commonly connected at a first node to both a driver circuit for providing a clock signal and a load capacitor, and operatively connectable to receive a delayed clock signal, comprising:

a gate control circuit having a first input operatively connected to the first node, having a second input operatively connectable to receive the delayed clock signal and having an output;
a gate circuit having a first input operatively connected to the output of said gate control circuit, having a second input and having an output operatively connected to the first node;
a boosting capacitor having a first terminal operatively connected to the second input of said gate control circuit and operatively connectable to receive the delayed clock signal and having a second terminal operatively connected to the second input of said gate circuit;
and
a charging circuit having an output operatively connected to the second terminal of said boosting capacitor.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/213,398Filed 5 Dec 1980
Priority: JP 54-1577515 Dec 1979
Granted: 3 May 1983
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H02M 3/07
Using resistors or capacitors, e.g. potential divider: using capacitors charged and discharged alternately by semiconductor devices with control…
G11C 5/145
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels:…
G11C 11/4076
For memory cells of the field-effect type: timing circuits
G11C 11/4085
Address circuits: word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge