Multi-planar electrode plasma etching

Abstract

Dry plasma etching of a plurality of planar thin-film semiconductor wafers is effected simultaneously and uniformly in a relatively small chamber enveloping a vertically-stacked array of laminar electrode sub-assemblies each of which includes a pair of oppositely-excited electrode plates tightly sandwiching a solid insulating layer of dielectric material, the parallel sub-assemblies being vertically separated to subdivide the chamber into a plurality of reactor regions where RF discharges can excite a normally inert ambient gas to develop reactive plasma for simultaneous planar plasma etching or reactive ion etching (RIE) of all wafers within the several regions. The upper plates of the electrode sub-assemblies, which support the wafers during etching, are at any instant all maintained at the same potential, whether RF or ground in the different modes of operation, and fluid coolant is forced through a distribution of internal passageways in those support plates; all lower plates of the pairs are simultaneously maintained at the opposite potential, whether ground or RF, and the intervening insulating dielectric layers in the sub-assemblies are relatively thin while at the same time providing critical electrical isolation and curbing spurious discharge without serious electrical mismatching. Uncomplicated transport of individual wafers between vertically-stacked positions in a cassette and the stacked array of etching regions is accomplished from below by a reciprocatable arm which is receivable within accommodating slots recessed into the upper cooled electrode plates alongside one edge of the stacked array; programmed vertical movements of the cassette and electrode array allow for appropriate loading and unloading of wafers, and for proper orientation of the reactor regions in relation to the enclosing chamber and associated equipment.

Dependencies are inferred from the claim text.