High speed dividing circuit

Apparatus for producing a quotient from a binary number dividend and a binary number divisor comprising:

• a data bus for sequential transmission of said dividend and said divider as parallel bit numbers,
• two's complement adder means connected to said data bus and adapted to receive said dividend and said divisor and to sense the sign bit to determine if the dividend and/or the divisor shall be complemented,
• a parallel dividend shift register coupled to said two's complement adder means for receiving and storing the dividend number from said adder means prior to a division operation,
• a parallel divisor register coupled to said two's complement adder means for receiving and storing the divisor number from said adder means prior to a division operation,
• a parallel adder having its inputs connected to the output of the divisor register and the output of said dividend shift register, said parallel adder having a sign position output,
• the output of said parallel adder being connected to the input of said dividend shift register,
• control means, coupled to said data bus and including a flag bit comparator for comparing the sign of the dividend and the divisor,
• quotient shift register means coupled to said control means and coupled to the sign position output of said parallel adder, and
• said control means being coupled to said adder means, said divisor register and said dividend shift register for producing timing signals for first loading the dividend number and then the divisor number from said adder means into said dividend and said divisor registers and subsequently initiating a dividing operation whereby, the number in said dividend shift register is added to the number in said divisor register and the resulting sign position output is processed and stored in said quotient register means.