Synchronously operatable PCM recording processor

A PCM recording processor comprising:

• an A/D converting means for converting an analog input signal to a digital signal;
• a recording means coupled to said A/D converting means for recording said digital signal on a recording medium;
• a reproducing means for reading out said digital signal from said recording medium;
• a D/A converting means coupled to said reproducing means for converting said digital signal to an analog signal;
• an A/D timing generating means comprising gates for controlling said A/D converting means;
• a D/A timing generating means comprising gates for controlling said D/A converting means;
• a first timing generating means comprising counters for providing timing signals to both said A/D timing generating means and said D/A timing generating means;
• a first synchronizing signal generator coupled to said first timing generating means for generating a first synchronizing signal;
• a first synchronizing signal port;
• a first switching means for (a) connecting an output of said first synchronizing signal generator to said first synchronizing signal port when said PCM recording processor is in a master mode and for (b) connecting said first synchronizing signal port to a reset terminal of said first timing generating means in order to reset said first timing generating means when said PCM recording processor is in a slave mode;
• a second timing generating means for controlling said recording means and for driving said recording medium;
• a second synchronizing signal generator coupled to said second timing generating means for generating a second synchronizing signal;
• a second synchronizing signal port;
• a second switching means for (a) connecting an output of said second synchronizing signal generator to said second synchronizing signal port when said PCM recording processor is in the master mode and for (b) connecting said second synchronizing signal port to a reset terminal of said second timing generator in order to reset said second timing generator when said PCM recording processor is in the slave mode;
• a clock generator for generating a first clock signal for said first timing generating means and a second clock signal for said second timing generator;
• a first clock signal port;
• a third switching means for (a) connecting said first clock signal to both said first clock signal port and said first timing generating means when said PCM recording processor is in the master mode and for (b) connecting said first clock signal port to said first timing generating means when said PCM recording processor is in the slave mode;
• a second clock signal port;
• and a fourth switching means for (a) connecting said second clock signal to both said second clock signal port and said second timing generator when said PCM recording processor is in the master mode and for (b) connecting said second clock signal port to said second timing generator when said PCM recording processor is in the slave mode.