Two stage etching process for through the substrate contacts
AssigneeWestinghouse Electric Corp.
InventorsJohn X. Przybysz, Michael C. Driver, Harvey C. Nathanson
Life of this patent
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Abstract
Electrical interconnection paths or vias are provided through relatively thick type III/V semiconductive substrates, such as gallium arsenide, to permit through the substrate electrical interconnection of planar transistor devices. The vias are etched in a two-step process which ensures that the via lateral dimensions are less than the transistor contacts with which they are aligned. The first step comprises selectively thinning the thick substrate from the back surface over an area which encompasses the transistor array formed in the front surface of the substrate. The second step is to etch the individual vias through this prior thinned substrate at areas aligned with the transistor contacts.
Claims4
Method of providing a plurality of electrical interconnection vias through an integrated circuit substrate wherein a plurality of transistor devices are formed on one side of the substrate with a plurality of transistor contacts disposed on the substrate surface in electrical contact with transistor regions, wherein the respective interconnection vias are aligned with and are smaller in area than the transistor contacts with which they are respectively aligned, which method comprises;
- (a) selectively thinning the substrate from the side opposed to the side on which the transistor devices and transistor contacts are disposed, which selectively thinned substrate area exceeds the transistor contact area;
- (b) etching through portions of the selectively thinned substrate area which is aligned with the transistor contacts to produce electrical interconnection vias of an area smaller than the transistor contact area.
Dependencies are inferred from the claim text.