Method of making double level polysilicon series transistor devices
AssigneeTexas Instruments Incorporated
InventorG. R. Mohan Rao
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Abstract
A plurality of MOS transistors are formed as an integrated semiconductor device, adjacent transistors sharing a common source/drain region which is created by the edges of inverted regions beneath the gates of the transistors. These gates are first and second level polysilicon, with the second partly overlapping the first. On the opposite ends, the source and drain regions are formed by diffusion using the oxide under the first and second level poly as the diffusion mask.
Claims9
A method of making a pair of adjacent semiconductor devices comprising the steps of applying a first layer on a face of a semiconductor body then patterning it to define an electrode of one of the devices, applying a second layer on said face and patterning it to define an electrode of the other of the semiconductor devices, the second layer partially overlapping the first layer, then introducing impurity material into the face using the first and second layers as a mask to create regions of the semiconductor devices.
A method of making a plurality of adjacent semiconductor devices comprising the steps of applying a first layer on a face of a semiconductor body then patterning it to define an electrode at least of one of the devices, applying a second layer on said face and patterning it to define an electrode of at least one other of the devices, the second layer partially overlapping the first layer and being insulated therefrom, then introducing impurity material into the face using the first and second layers as a mask to create a region of at least two of the devices.
Dependencies are inferred from the claim text.